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PDF 5P49V5943 Data sheet ( Hoja de datos )
| Número de pieza | 5P49V5943 | |
| Descripción | Programmable Clock Generator | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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Programmable Clock Generator
5P49V5943
DATASHEET
Description
The 5P49V5943 is a programmable clock generator intended
for high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I2C
interface. This is IDTs fifth generation of programmable clock
technology (VersaClock® 5).
The frequencies are generated from a single input reference
clock.
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I2C
addresses to allow multiple devices to be used in a system.
Pin Assignment
CLKIN
CLKINB
VDDA
VDD
SD/OE
20 19 18 17 16
1 15
2 14
3
EPAD
13
4 12
5 11
6 7 8 9 10
VDDO1
OUT1
OUT1B
GND
GND
20-pin VFQFPN
Features
• Generates up to two independent output frequencies
• High performance, low phase noise PLL, <0.7 ps RMS
typical phase jitter on outputs:
– PCIe Gen1, 2, 3 compliant clock capability
– USB 3.0 compliant clock capability
– 1 GbE and 10 GbE
• Two fractional output dividers (FODs)
• Independent Spread Spectrum capability on each output
pair
• Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
• I2C serial programming interface
• One reference LVCMOS output clock
• Two universal output pairs:
– Each configurable as one differential output pair or two
LVCMOS outputs
• I/O Standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
– Differential I/Os - LVPECL, LVDS and HCSL
• Input frequency ranges:
– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,
CLKINB) – 1MHz to 350MHz
• Output frequency ranges:
– LVCMOS Clock Outputs – 1MHz to 200MHz
– LVDS, LVPECL, HCSL Differential Clock Outputs –
1MHz to 350MHz
• Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output pair
• Programmable loop bandwidth
• Programmable output to output skew
• Programmable slew rate control
• Individual output enable/disable
• Power-down mode
• 1.8V, 2.5V or 3.3V core VDDD, VDDA
• Available in 20-pin VFQFPN 3mm x 3mm package
• -40° to +85°C industrial temperature operation
5P49V5943 NOVEMBER 11, 2016
1 ©2015 Integrated Device Technology, Inc.
1 page  
Reference Clock Input Pins
The 5P49V5943 supports one reference clock input. The
clock input (CLKIN, CLKINB) is a fully differential input that
only accepts a reference clock. The differential input accepts
differential clocks from all the differential logic types and can
also be driven from a single ended clock on one of the input
pins.
OTP Interface
The 5P49V5943 can also store its configuration in an internal
OTP. The contents of the device's internal programming
registers can be saved to the OTP by setting burn_start
(W114[3]) to high and can be loaded back to the internal
programming registers by setting usr_rd_start(W114[0]) to
high.
To initiate a save or restore using I2C, only two bytes are
transferred. The Device Address is issued with the read/write
bit set to “0”, followed by the appropriate command code. The
save or restore instruction executes after the STOP condition
is issued by the Master, during which time the 5P49V5943 will
not generate Acknowledge bits. The 5P49V5943 will
acknowledge the instructions after it has completed execution
of them. During that time, the I2C bus should be interpreted as
busy by all other users of the bus.
On power-up of the 5P49V5943, an automatic restore is
performed to load the OTP contents into the internal
programming registers. The 5P49V5943 will be ready to
accept a programming instruction once it acknowledges its
7-bit I2C address.
Availability of Primary and Secondary I2C addresses to allow
programming for multiple devices in a system. The I2C slave
address can be changed from the default 0xD4 to 0xD0 by
programming the I2C_ADDR bit D0. VersaClock 5
Programming Guide provides detailed I2C programming
guidelines and register map.
SD/OE Pin Function
The polarity of the SD/OE signal pin can be programmed to be
either active HIGH or LOW with the SP bit (W16[1]). When SP
is “0” (default), the pin becomes active LOW and when SP is
“1”, the pin becomes active HIGH. The SD/OE pin can be
configured as either to shutdown the PLL or to enable/disable
the outputs. The SH bit controls the configuration of the
SD/OE pin The SH bit needs to be high for SD/OE pin to be
configured as SD.
SP
SD/OE Input
SH
OEn
Global Shutdown
OSn
OUTn
5P49V5943 DATASHEET
outputs are driven High/low, and the single-ended LVCMOS
outputs are driven low. When configured as OE, and outputs
are disabled, the outputs are driven high/low.
Table 4: SD/OE Pin Function Truth Table
SH bit SP bit OSn bit OEn bit SD/OE
OUTn
00
0
x
x Tri-state2
00
1
0 x Output active
00
1
1 0 Output active
00
1
1 1 Output driven High Low
01
0
x
x Tri-state2
01
1
0 x Output active
01
1
1 0 Output driven High Low
01
1
1 1 Output active
10
0
x
0 Tri-state2
10
1
0 0 Output active
10
1
1 0 Output active
11
0
x
0 Tri-state2
11
1
0 0 Output active
11
1
1 0 Output driven High Low
1x
x
x 1 Output driven High Low 1
Note 1 : Global Shutdown
Note 2 : Tri-state regardless of OEn bits
Output Divides
Each output divide block has a synchronizing POR pulse to
provide startup alignment between outputs divides. This
allows alignment of outputs for low skew performance. This
low skew would also be realized between outputs that are
both integer divides from the VCO frequency. This phase
alignment works when using configuration with SEL1, SEL0.
For I2C programming, I2C reset is required.
An output divide bypass mode (divide by 1) will also be
provided, to allow multiple buffered reference outputs.
Each of the two output divides are comprised of a 12 bit
integer counter, and a 24 bit fractional counter. The output
divide can operate in integer divide only mode for improved
performance, or utilize the fractional counters to generate a
clock frequency accurate to 50 ppb.
Each of the output divides also have structures capable of
independently generating spread spectrum modulation on the
frequency output.
The Output Divide also has the capability to apply a spread
modulation to the output frequency. Independent of output
frequency, a triangle wave modulation between 30 and 63kHz
may be generated.
For all outputs, there is a bypass mode, to allow the output to
behave as a buffered copy of the input.
When configured as SD, device is shut down, differential
NOVEMBER 11, 2016
5
PROGRAMMABLE CLOCK GENERATOR
5 Page 
5P49V5943 DATASHEET
Table 12: DC Electrical Characteristics for 3.3V LVCMOS (VDDO = 3.3V±5%, TA = -40°C to +85°C)1
Symbol
VOH
VOL
IOZDD
IOZDD
VIH
VIL
VIH
VIL
TR/TF
Parameter
Test Conditions
Output HIGH Voltage
IOH = -15mA
Output LOW Voltage
IOL = 15mA
Output Leakage Current (OUT1~4) Tri-state outputs, VDDO = 3.465V
Output Leakage Current (OUT0) Tri-state outputs, VDDO = 3.465V
Input HIGH Voltage
Single-ended inputs - SD/OE
Input LOW Voltage
Single-ended inputs - SD/OE
Input HIGH Voltage
Single-ended input OUT0_SEL_I2CB
Input LOW Voltage
Single-ended input OUT0_SEL_I2CB
Input Rise/Fall Time
SD/OE, SEL1/SDA, SEL0/SCL
Min
2.4
0.7xVDDD
GND - 0.3
2
GND - 0.3
Typ
Max
Unit
VDDO
V
0.4 V
5 µA
30 µA
VDDD + 0.3 V
0.3xVDDD V
VDDO0 + 0.3 V
0.4 V
300 nS
1. See “Recommended Operating Conditions” table.
Table 13: DC Electrical Characteristics for 2.5V LVCMOS (VDDO = 2.5V±5%, TA = -40°C to +85°C)
Symbol
VOH
VOL
IOZDD
IOZDD
VIH
VIL
VIH
VIL
Parameter
Test Conditions
Output HIGH Voltage
IOH = -12mA
Output LOW Voltage
IOL = 12mA
Output Leakage Current (OUT1~4) Tri-state outputs, VDDO = 2.625V
Output Leakage Current (OUT0) Tri-state outputs, VDDO = 2.625V
Input HIGH Voltage
Single-ended inputs - SD/OE
Input LOW Voltage
Single-ended inputs - SD/OE
Input HIGH Voltage
Single-ended input OUT0_SEL_I2CB
Input LOW Voltage
Single-ended input OUT0_SEL_I2CB
Min
0.7xVDDO
0.7xVDDD
GND - 0.3
1.7
GND - 0.3
Typ
Max
Unit
V
0.4 V
5 µA
30 µA
VDDD + 0.3 V
0.3xVDDD V
VDDO0 + 0.3 V
0.4 V
TR/TF
Input Rise/Fall Time
SD/OE, SEL1/SDA, SEL0/SCL
300 nS
Table 14: DC Electrical Characteristics for 1.8V LVCMOS (VDDO = 1.8V±5%, TA = -40°C to +85°C)
Symbol
VOH
VOL
IOZDD
IOZDD
VIH
VIL
VIH
VIL
TR/TF
Parameter
Test Conditions
Output HIGH Voltage
IOH = -8mA
Output LOW Voltage
IOL = 8mA
Output Leakage Current (OUT1~4) Tri-state outputs, VDDO = 3.465V
Output Leakage Current (OUT0) Tri-state outputs, VDDO = 3.465V
Input HIGH Voltage
Single-ended inputs - SD/OE
Input LOW Voltage
Single-ended inputs - SD/OE
Input HIGH Voltage
Single-ended input OUT0_SEL_I2CB
Input LOW Voltage
Single-ended input OUT0_SEL_I2CB
Input Rise/Fall Time
SD/OE, SEL1/SDA, SEL0/SCL
Min
Typ
Max
Unit
0.7 xVDDO
VDDO
V
0.25 x VDDO V
5 µA
30 µA
0.7 * VDDD
VDDD + 0.3 V
GND - 0.3
0.3 * VDDD V
0.65 * VDDO0
VDDO0 + 0.3 V
GND - 0.3
0.4 V
300 nS
NOVEMBER 11, 2016
11 PROGRAMMABLE CLOCK GENERATOR
11 Page | ||
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| PDF Descargar | [ Datasheet 5P49V5943.PDF ] | |
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