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ICS8305I 데이터시트 PDF




Integrated Device Technology에서 제조한 전자 부품 ICS8305I은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 ICS8305I 기능
기능 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
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ICS8305I 데이터시트, 핀배열, 회로
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS8305I is a low skew, 1-to-4, Differential/LVCMOS-to-
LVCMOS/LVTTL Fanout Buffer. The ICS8305I has selectable
clock inputs that accept either differential or single ended
input levels. The clock enable is internally synchronized to
eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin. Outputs are
forced LOW when the clock is disabled. A separate output
enable pin controls whether the outputs are in the active or
high impedance state.
Guaranteed output and part-to-part skew characteristics make
the ICS8305I ideal for those applications demanding well de-
fined performance and repeatability.
FEATURES
• 4 LVCMOS/LVTTL outputs
• Selectable differential or LVCMOS/LVTTL clock inputs
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• LVCMOS_CLK supports the following input types:
LVCMOS, LVTTL
• Maximum output frequency: 350MHz
• Output skew: 40ps (maximum)
• Part-to-part skew: 700ps (maximum)
Additive phase jitter, RMS: 0.04ps (typical)
• 3.3V core, 3.3V, 2.5V or 1.8V output operating supply
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
CLK_EN
LVCMOS_CLK
CLK
nCLK
CLK_SEL
00
11
D
Q
LE
OE
PIN ASSIGNMENT
GND 1 16 Q0
OE 2
1 5 VDDO
VDD 3
14 Q1
CLK_EN 4 13 GND
CLK 5 12 Q2
Q0
nCLK 6
1 1 VDDO
CLK_SEL 7 10 Q3
Q1
LVCMOS_CLK 8
9 GND
Q2 ICS8305I
16-Lead TSSOP
4.4mm x 3.0mm x 0.92mm package body
Q3 G Package
Top View
8305AGI
www.idt.com
1
REV. B SEPTEMBER 17, 2012




ICS8305I pdf, 반도체, 판매, 대치품
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
Inputs, VI
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
4.6V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
89°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
VDD Core Supply Voltage
3.135
3.135
VDDO
Output Supply Voltage
2.375
1.65
IDD Power Supply Current
IDDO Output Supply Current
Typical
3.3
3.3
2.5
1.8
Maximum
3.465
3.465
2.625
1.95
21
5
Units
V
V
V
V
mA
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
Input
CLK_EN, CLK_SEL, OE
High Voltage LVCMOS_CLK
VIL
Input
CLK_EN, CLK_SEL, OE
Low Voltage LVCMOS_CLK
2
VDD + 0.3
V
2
VDD + 0.3
V
-0.3 0.8 V
-0.3 1.3 V
IIH
Input
CLK_EN, CLK_SEL, OE
High Current LVCMOS_CLK
VDD = VIN = 3.465V
VDD = VIN = 3.465V
5
150
IIL
Input
CLK_EN, CLK_SEL, OE
Low Current LVCMOS_CLK
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
-150
-5
VDDO = 3.3V ± 5%
2.6
VOH Output High Voltage; NOTE 1
VDDO = 2.5V ± 5%
1.8
VDDO = 1.8V ± 0.15V
VDDO - 0.3
VDDO = 3.3V ± 5%
0.5
VOL Output Low Voltage; NOTE 1
VDDO = 2.5V ± 5%
0.5
VDDO = 1.8V ± 0.15V
0.4
IOZL Output Tristate Current Low
-5
IOZH Output Tristate Current High
5
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit.
µA
µA
µA
µA
V
V
V
V
V
V
µA
µA
8305AGI
www.idt.com
4
REV. B SEPTEMBER 17, 2012

4페이지










ICS8305I 전자부품, 판매, 대치품
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
Input/Output Additive
Phase Jitter at 155.52MHz
= 0.04ps typical
10k 100k 1M
OFFSET FROM CARRIER FREQUENCY (HZ)
10M
100M
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
8305AGI
www.idt.com
7
REV. B SEPTEMBER 17, 2012

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