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PDF ICS8543I Data sheet ( Hoja de datos )
| Número de pieza | ICS8543I | |
| Descripción | Differential-to-LVDS Fanout Buffer | |
| Fabricantes | Integrated Device Technology | |
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Low Skew, 1-to-4,
Differential-to-LVDS Fanout Buffer
ICS8543I
DATA SHEET
General Description
The ICS8543I is a low skew, high performance 1-to-4 Differen-
tial-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential
Signaling (LVDS) the ICS8543I provides a low power, low noise, so-
lution for distributing clock signals over controlled impedances of
100. The ICS8543I has two selectable clock inputs. The CLK,
nCLK pair can accept most standard differential input levels. The
PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels.
The clock enable is internally synchronized to eliminate runt pulses
on the outputs during asynchronous assertion/deassertion of the
clock enable pin.
Guaranteed output and part-to-part skew characteristics make the
ICS8543I ideal for those applications demanding well defined perfor-
mance and repeatability.
Features
• Four differential LVDS output pairs
• Selectable differential CLK/nCLK or LVPECL clock inputs
• CLK/nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• PCLK/nPCLK pair can accept the following differential input
levels: LVPECL, CML, SSTL
• Maximum output frequency: 650MHz
• Translates any single-ended input signals to LVDS levels with
resistor bias on nCLK input
• Additive phase Jitter, RMS: 0.164ps (typical)
• Output skew: 40ps (maximum)
• Part-to-part skew: 600ps (maximum)
• Propagation delay: 2.6ns (maximum)
• Full 3.3Vsupply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free packages
Block Diagram
CLK_EN Pullup
CLK Pulldown
nCLK Pullup
PCLK Pulldown
nPCLK Pullup
CLK_SEL Pulldown
00
1
1
D
Q
LE
OE Pullup
Pin Assignment
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
GND
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
OE
GND
VDD
1
2
3
4
5
6
7
8
9
10
20 Q0
19 nQ0
18 VDD
17 Q1
16 nQ1
15 Q2
14 nQ2
13 GND
12 Q3
11 nQ3
ICS8543I
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
ICS8543BGI REVISION E NOVEMBER 15, 2012
1
©2012 Integrated Device Technology, Inc.
1 page  
ICS8543I Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Table 4D. LVPECL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
IIH
IIL
VPP
VCMR
Input High Current
PCLK
nPCLK
Input Low Current
PCLK
nPCLK
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
VDD = VIN = 3.465V
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
-5
-150
0.3
1.5
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Table 4E. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VOD
VOD
VOS
VOS
IOz
IOFF
IOSD
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
High Impedance Leakage
Power Off Leakage
Differential Output Short Circuit
Current
200
1.125
-10
-20
IOS Output Short Circuit Current
VOH Output Voltage High
VOL Output Voltage Low
0.9
Typical
Typical
280
0
1.25
5
±1
-3.5
-3.5
1.34
1.06
Maximum
150
5
1
VDD
Units
µA
µA
µA
µA
V
V
Maximum
360
40
1.375
25
+10
+20
-5
-5
1.6
Units
mV
mV
V
mV
µA
µA
mA
mA
V
V
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Parameter Symbol
Test Conditions
fMAX
tjit
Maximum Output Frequency
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
153.6MHz, Integration
Range: 12kHz – 20MHz
tPD
tsk(o)
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
ƒ 650MHz
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
odc
20% to 80% @ 50MHz
Minimum
1.5
150
45
Typical
0.164
50
Maximum
650
2.6
40
600
450
55
Units
MHz
ps
ns
ps
ps
ps
%
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the differential output crosspoints.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential crosspoints.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS8543BGI REVISION E NOVEMBER 15, 2012
5
©2012 Integrated Device Technology, Inc.
5 Page 
ICS8543I Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both signals must meet the VPP and VCMR input
requirements. Figures 4A to 4F show interface examples for the S
PCLK/nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
3.3V
CML
Zo = 50Ω
Zo = 50Ω
3.3V
R1 R2
50Ω 50Ω
3.3V
PCLK
nPCLK
LVPECL
Input
3.3V
CML Built-In Pullup
Zo = 50Ω
Zo = 50Ω
3.3V
R1
100Ω
PCLK
nPCLK
LVPECL
Input
Figure 4A. PCLK/nPCLK Input Driven by a
CML Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
125Ω
R4
125Ω
3.3V
PCLK
nPCLK
LVPECL
R1 R2
84Ω 84Ω
Input
Figure 4B. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
3.3V
3.3V LVPECL
Zo = 50Ω
Zo = 50Ω
R5
100 - 200
R6
100 - 200
3.3V
R3
84
C1
R4
84
C2
R1 R2
125 125
3.3V
PCLK
nPCLK
LVPECL
Input
Figure 4C. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
2.5V
SSTL
Zo = 60Ω
Zo = 60Ω
2.5V
R3 R4
120 120
3.3V
PCLK
R1 R2
120 120
nPCLK
LVPECL
Input
Figure 4D. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
3.3V
LVDS
Zo = 50Ω
Zo = 50Ω
3.3V
R1
100Ω
PCLK
nPCLK
LVPECL
Input
Figure 4E. PCLK/nPCLK Input Driven by an
SSTL Driver
ICS8543BGI REVISION E NOVEMBER 15, 2012
Figure 4F. PCLK/nPCLK Input Driven by a
3.3V LVDS Driver
11 ©2012 Integrated Device Technology, Inc.
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ICS8543I.PDF ] | |
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