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ICS854S054I 데이터시트 PDF




Integrated Device Technology에서 제조한 전자 부품 ICS854S054I은 전자 산업 및 응용 분야에서
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부품번호 ICS854S054I 기능
기능 4:1 Differential-to-LVDS Clock Multiplexer
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ICS854S054I 데이터시트, 핀배열, 회로
4:1 Differential-to-LVDS Clock Multiplexer
ICS854S054I
DATA SHEET
General Description
The ICS854S054I is a 4:1 Differential-to-LVDS Clock Multiplexer
which can operate up to 2.5GHz. The ICS854S054I has 4 selectable
differential clock inputs. The PCLK, nPCLK input pairs can accept
LVPECL, LVDS or CML levels. The fully differential architecture and
low propagation delay make it ideal for use in clock distribution
circuits. The select pins have internal pulldown resistors. The SEL1
pin is the most significant bit and the binary number applied to the
select pins will select the same numbered data input (i.e., 00 selects
PCLK0, nPCLK0).
Features
High speed 4:1 differential multiplexer
One differential LVDS output pair
Four selectable differential PCLK, nPCLK input pairs
PCLKx, nPCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, CML
Maximum output frequency: 2.5GHz
Translates any single ended input signal to LVDS levels with
resistor bias on nPCLKx input
Additive phase jitter, RMS: 0.147ps (typical)
Part-to-part skew: 300ps (maximum)
Propagation delay: 700ps (maximum)
Supply voltage range: 3.135V to 3.465V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
PCLK0 Pulldown
nPCLK0 Pullup/Pulldown
PCLK1 Pulldown
nPCLK1 Pullup/Pulldown
PCLK2 Pulldown
nPCLK2 Pullup/Pulldown
PCLK3 Pulldown
nPCLK3 Pullup/Pulldown
00 (default)
01
10
11
SEL1 Pulldown
SEL0 Pulldown
ICS854S054AGI REVISION A SEPTEMBER 28, 2012
Pin Assignment
PCLK0
nPCLK0
PCLK1
nPCLK1
VDD
SEL0
SEL1
GND
1
2
3
4
5
6
7
8
16 VDD
15 Q
14 nQ
13 GND
12 nPCLK3
11 PCLK3
10 nPCLK2
9 PCLK2
ICS854S054I
16-Lead TSSOP
Q 5.0mm x 4.4mm x 0.92mm package body
nQ G Package
Top View
1 ©2012 Integrated Device Technology, Inc.




ICS854S054I pdf, 반도체, 판매, 대치품
ICS854S054I Data Sheet
4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Table 4D. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VOD
VOD
VOS
VOS
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
247
1.125
Typical
380
1.28
Maximum
454
50
1.375
50
Units
mV
mV
V
mV
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
fOUT
tPD
tjit(Ø)
Output Frequency
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter,
RMS; Refer to Additive Phase
Jitter Section
155.52MHz, Integration Range:
12kHz – 20MHz
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
tsk(i)
Input Skew
tR / tF
MUXISOLATION
Output Rise/Fall Time
MUX Isolation; NOTE 4
20% to 80%
155.52MHz, VPP = 800mV
Minimum
295
70
Typical
470
0.147
10
150
86
Maximum
2.5
700
Units
GHz
ps
ps
300 ps
50 ps
250 ps
dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured 1.0GHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Q, nQ output measured differentially. See Parameter Measurement Information for MUX Isolation diagram.
ICS854S054AGI REVISION A SEPTEMBER 28, 2012
4
©2012 Integrated Device Technology, Inc.

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ICS854S054I 전자부품, 판매, 대치품
ICS854S054I Data Sheet
Parameter Measurement Information, continued
4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
nQ
20%
Q
80%
tR
80%
tF
VOD
20%
VDD
DC Input LVDS
out
100
out
Output Rise/Fall Time
VDD
DC Input LVDS
Differential Output Voltage Setup
out
out VOS/VOS
Offset Voltage Setup
ICS854S054AGI REVISION A SEPTEMBER 28, 2012
7
©2012 Integrated Device Technology, Inc.

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ICS854S054I

4:1 Differential-to-LVDS Clock Multiplexer

Integrated Device Technology
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