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PDF ICS8714008I Data sheet ( Hoja de datos )
| Número de pieza | ICS8714008I | |
| Descripción | Zero Delay Buffer/ Clock Generator | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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FemtoClock® Zero Delay Buffer/ Clock
Generator for PCI Express™ and Ethernet
ICS8714008I
DATASHEET
General Description
The ICS8714008I is Zero-Delay Buffer/Frequency Multiplier with
eight differential HCSL output pairs, and uses external feedback
(differential feedback input and output pairs) for “zero delay” clock
regeneration. In PCI Express and Ethernet applications, 100MHz
and 125MHz are the most commonly used reference clock
frequencies and each of the eight output pairs can be independently
set for either 100MHz or 125MHz. With an output frequency range of
98MHz to 165MHz, the device is also suitable for use in a variety of
other applications such as Fibre Channel (106.25MHz) and XAUI
(156.25MHz). The M-LVDS Input/Output pair is useful in backplane
applications when the reference clock can either be local (on the
same board as the ICS8714008I) or remote via a backplane
connector. In output mode, an input from a local reference clock
applied to the CLK, nCLK input pins is translated to M-LVDS and
driven out to the MLVDS, nMLVDS pins. In input mode, the internal
M-LVDS driver is placed in High-impedance state using the
OE_MLVDS pin and MLVDS, nMLVDS pin then becomes an input
(e.g. from a backplane).
The ICS8714008I uses very low phase noise FemtoClock
technology, thus making it ideal for such applications as PCI Express
Generation 1, 2 and 3 as well as for Gigabit Ethernet, Fibre Channel,
and 10 Gigabit Ethernet. It is packaged in a 56-VFQFN package
(8mm x 8mm).
Features
• Eight 0.7V differential HCSL output pairs, individually selectable
for 100MHz or 125MHz for PCIe and Ethernet applications
• One differential clock input pair CLK, nCLK can accept the
following differential input levels: LVPECL, LVDS, M-LVDS,
LVHSTL, HCSL
• One M-LVDS I/O pair (MLVDS, nMLVDS)
• Output frequency range: 98MHz - 165MHz
• Input frequency range: 19.6MHz - 165MHz
• VCO range: 490MHz - 660MHz
• PCI Express (2.5 Gb/s), Gen 2 (5 Gb/s), and Gen 3 (8 Gb/s)
jitter compliant
• External feedback for “zero delay” clock regeneration
• RMS phase jitter @ 125MHz (1.875MHz – 20MHz):
0.59ps (typical)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHs 6) packaging
Pin Assignment
VDD
OE_MLVDS
MLVDS
nMLVDS
GND
PLL_SEL
VDD
nc
FBO_DIV
MR
OE0
OE1
OE2
GND
56 55 54 53 52 51 50 49 48 47 46 45 44 43
1 42
2 41
3 40
4 39
5 38
6 37
7 36
8 35
9 34
10 33
11 32
12 31
13 30
14 29
15 17 18 21 24 25 27 28
VDD
Q2
nQ2
Q3
nQ3
VDD
Q4
nQ4
Q5
nQ5
FBOUT
nFBOUT
VDD
IREF
ICS8714008DKI REVISION A NOVEMBER 25, 2013
ICS8714008I
56-Lead VFQFN
8mm x 8mm x 0.925mm package body
4.5mm x 5.2mm ePad size
K Package
Top View
1 ©2013 Integrated Device Technology, Inc.
1 page  
ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Table 1. Pin Descriptions
Number
Name
Type
Description
54
nCLK
Input
Pullup/ Inverting differential clock input.
Pulldown Accepts LVPECL, HCSL, LVDS, M-LVDS and HSTL input levels.
55
PDIV0
Input
Pulldown
Input Divide Select 0. Together with PDIV1 determines the input divider
value. Refer to Table 3F. LVCMOS/LVTTL Interface levels.
56
PDIV1
Input
Pulldown
Input Divide Select 1. Together with PDIV0 determines the input divider
value. Refer to Table 3F. LVCMOS/LVTTL Interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLUP
RPULLDOWN
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
ICS8714008DKI REVISION A NOVEMBER 25, 2013
5
©2013 Integrated Device Technology, Inc.
5 Page 
ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
Table 5B. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
fOUT
tjit(cc)
Output Frequency
Cycle-to-Cycle Jitter; NOTE 1
tsk(o)
Output Skew; NOTE 1, 2
Outputs measured Q[0:7], nQ[0:7]
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3, 4
125MHz, Integration Range:
1.875MHz – 20MHz
100MHz, Integration Range:
1.875MHz – 20MHz
tL
VMAX
PLL Lock Time
Absolute Max Output Voltage;
NOTE 5, 6
VMIN
Absolute Min Output Voltage;
NOTE 5, 7
VRB
tSTABLE
Ringback Voltage; NOTE 8, 9
Time before VRB is allowed;
NOTE 8, 9
VCROSS
Absolute Crossing Voltage;
NOTE 5, 10, 11
VCROSS
Total Variation of VCROSS over
all edges; NOTE 5, 10, 12
Rise/Fall Rising/Falling Edge Rate;
Edge Rate NOTE 8, 13
Measured between
-150mV to +150mV
odc Output Duty Cycle; NOTE 14
Minimum
98
-300
-100
500
150
0.6
45
Typical
35
100
0.587
0.592
Maximum
165
80
210
Units
MHz
ps
ps
ps
100
1150
ps
ms
mV
mV
100 mV
ps
550 mV
140 mV
4 V/ns
55 %
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. Characterized with configurations in Table 3A.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 3: Refer to the Phase Noise plots.
NOTE 4: Measurements depend on input source used.
NOTE 5: Measurement taken from single-ended waveform.
NOTE 6: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 7: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 8: Measurement taken from a differential waveform.
NOTE 9: tSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the VRB ±100mV differential range. See Parameter Measurement Information Section.
NOTE 10: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.
See Parameter Measurement Information Section
NOTE 11: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement. See Parameter Measurement Information Section.
NOTE 12: Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the
VCROSS for any particular system. See Parameter Measurement Information Section.
NOTE 13: Measured from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic
through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
See Parameter Measurement Information Section.
NOTE 14: Input duty cycle must be 50%.
ICS8714008DKI REVISION A NOVEMBER 25, 2013
11
©2013 Integrated Device Technology, Inc.
11 Page | ||
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