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기능 Dual Synchronous Ethernet Line Card PLL
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IDT82V3396 데이터시트, 핀배열, 회로
Dual Synchronous Ethernet Line Card
PLL
Short Form Datasheet
IDT82V3396
FEATURES
HIGHLIGHTS
• Dual PLL chip:
Provides node clock for ITU-T G.8261/G.8262 Synchronous
Ethernet (SyncE)
Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-4) jitter
generation requirements
Provides node clocks for Cellular and WLL base-station (GSM
and 3G networks)
Provides clocks for 1 Gigabit and 10 Gigabit Ethernet applica-
tions
MAIN FEATURES
• Employs PLL architecture to feature excellent jitter performance
and minimize the number of external components
• Integrates 2 DPLLs; one can be used on the transmit path and the
other on the receive path
• Supports programmable DPLL bandwidth: 18 Hz, 35 Hz, 70 Hz and
560 Hz
• Provides OUT1~OUT6 output clock frequencies up to 644.53125
MHz
Includes 25MHz, 125 MHz and 156.25 MHz for CMOS outputs
Includes 25.78125MHz, 128.90625 MHz and 161.1328125 MHz
for CMOS outputs
Includes 25MHz, 125 MHz, 156.25 MHz, 312.5 MHz and 625
MHz for differential outputs
Includes 25.78125 MHz, 128.90625 MHz, 161.1328125 MHz,
322.265625 MHz and 644.53125 MHz for differential outputs
• Provides IN1~IN6 input clock frequencies cover from 2 kHz to
156.25 MHz
• Supports Forced or Automatic operating mode switch controlled by
an internal state machine. It supports Free- Run, Locked and Hold-
over modes
• Supports manual and automatic selected input clock switch
• Supports automatic hitless selected input clock switch on clock fail-
ure
• Supports three types of input clock sources: recovered clock from
STM-N or OC-n, PDH network synchronization timing and external
synchronization reference timing
• Provides a 2 kHz, 4 kHz, or 8 kHz frame sync input signal, and a 2
kHz or 8 kHz frame sync output signals
• Provides a 1PPS sync input signal and a 1PPS sync output signal
• Provides output clocks for BITS, GPS, 3G, GSM, etc.
• Supports PECL/LVDS and CMOS input/output technologies
• Supports master clock calibration
• Supports Telcordia GR-1244-CORE, Telcordia GR-253-CORE,
ITU-T G.812, ITU-T G.8262. ITU-T G.813 and ITU-T G.783 Recom-
mendations
OTHER FEATURES
• I2C and Serial microprocessor interface modes
• IEEE 1149.1 JTAG Boundary Scan
• Single 3.3 V operation with 5 V tolerant CMOS I/Os
• 72-pin QFN package, green package options available
APPLICATIONS
• 1 Gigabit Ethernet and 10 Gigabit Ethernet
• BITS / SSU
• SMC / SEC (SONET / SDH)
• DWDM cross-connect and transmission equipment
• Synchronous Ethernet equipment
• Central Office Timing Source and Distribution
• Core and access IP switches / routers
• Gigabit and Terabit IP switches / routers
• IP and ATM core switches and access equipment
• Cellular and WLL base-station node clocks
• Broadband and multi-service access equipment
The Short Form Datasheet presented herein represents a product currently in design or being considered for design. The noted characteristics are design targets. Integrated
Device Technologies, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
2013 Integrated Device Technology, Inc.
1
February 4, 2013
DSC-7238/-




IDT82V3396 pdf, 반도체, 판매, 대치품
IDT82V3396 SHORT FORM DATASHEET
1 PIN ASSIGNMENT
DUAL SYNCHRONOUS ETHERNET LINE CARD PLL
VSSA
VC4
VSSA1
VDDA1
INT_REQ
OSCI
VSSA2
VDDA2
VDDA3
VSSA3
VSSA4
VDDA4
IC
VDDA5
VSSA5
VC0
VSS_DIFF
VDD_DIFF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
IDT82V3396
54 SCLK/I2C_SCL
53 I2C_AD2
52 I2C_AD1
51 CS/I2CAD0
50 SDI
49 CLKE
48 TMS
47 VSSD1
46 VDDD1
45 MPU_MODE
44 TRST
43 VDDD1
42 DPLL1_LOCK
41 DPLL2_LOCK
40 IN6
39 IN5
38 EX_SYNC2
37 VDDD1
Figure 2. Pin Assignment (Top View)
Pin Assignment
4 February 4, 2013

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IDT82V3396 전자부품, 판매, 대치품
IDT82V3396 SHORT FORM DATASHEET
DUAL SYNCHRONOUS ETHERNET LINE CARD PLL
Table 1: Pin Description (Continued)
Name
Pin No.
I/O
CLKE
49
I/O
pull-down
Type
CMOS
Description 1, 2
CLKE: SCLK Active Edge Selection
In Serial mode, this pin is an input, it selects the active edge of SCLK to update the SDO:
High - The falling edge;
Low - The rising edge.
SDI
SDO / I2C_SDA
I2C_AD1
I2C_AD2
SCLK / I2C_SCL
TRST
TMS
TCK
TDI
TDO
VDDD1
VDDD2
50
59
52
53
54
44
48
56
58
57
37,43, 46, 61
65
I/O
pull-down
CMOS
SDI: Serial Data Input
In Serial mode, this pin is used as the serial data input. Address and data on this pin are seri-
ally clocked into the device on the rising edge of SCLK.
I/O
pull-down
I
pull-up
I
pull-up
I
pull-down
I
pull-down
I
pull-up
I
pull-down
I
pull-up
O
Power
Power
CMOS
CMOS
CMOS
CMOS
SDO: Serial Data Output
In Serial mode, this pin is used as the serial data output. Data on this pin is serially clocked
out of the device on the active edge of SCLK.
I2C_SDA: Serial Data Input/Output
In I2C mode, this pin is used as the input/output for the serial data.
I2C_AD1: Device Address Bit 1
In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface.
In Serial mode, this pin should be connected to ground.
I2C_AD2: Device Address Bit 2
In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface.
In Serial mode, this pin should be connected to ground.
SCLK: Shift Clock
In Serial mode, a shift clock is input on this pin.
Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated
on the active edge of SCLK. The active edge is determined by the CLKE.
I2C_SCL: Serial Clock Line
In I2C mode, the serial clock is input on this pin.
JTAG (per IEEE 1149.1)
CMOS
CMOS
CMOS
CMOS
CMOS
TRST: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port.
This pin should be connected to ground when JTAG is not used.
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK.
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely
retain their state.
TDI: JTAG Test Data Input
The test data are input on this pin. They are clocked into the device on the rising edge of
TCK.
TDO: JTAG Test Data Output
The test data are output on this pin. They are clocked out of the device on the falling edge of
TCK.
TDO pin outputs a high impedance signal except during the process of data scanning.
This pin can indicate the interrupt of T0 selected input clock fail, as determined by the LOS_-
FLAG_ON_TDO bit (b6, 0BH).
Power & Ground
- VDDD1: Digital Core Power.
- VDDD2: CMOS CLK Output Power
Pin Description
7 February 4, 2013

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IDT82V3396

Dual Synchronous Ethernet Line Card PLL

Integrated Device Technology
Integrated Device Technology

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