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IDT82V3910 데이터시트 PDF




Integrated Device Technology에서 제조한 전자 부품 IDT82V3910은 전자 산업 및 응용 분야에서
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부품번호 IDT82V3910 기능
기능 Synchronous Ethernet SETS
제조업체 Integrated Device Technology
로고 Integrated Device Technology 로고


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IDT82V3910 데이터시트, 핀배열, 회로
Synchronous Ethernet SETS
for 10GbE and 40GbE
IDT82V3910
Short Form Datasheet
FEATURES
HIGHLIGHTS
• Jitter generation <0.3 ps RMS (10 kHz to 20 MHz), meets jitter gen-
eration requirements of leading PHYs supporting 10GBASE-R,
10GBASE-W, 40GBASE-R, OC-192 and STM-64
• Features 0.5 mHz to 35 Hz bandwidth
• Provides node clock for ITU-T G.8261/G.8262 Synchronous Ether-
net (SyncE)
• Provides node clocks for Cellular and WLL base-station (GSM and
3G networks)
• Provides clocks for DSL access concentrators (DSLAM), especially
for Japan TCM-ISDN network timing based ADSL equipments
• Provides clocks for 1 Gigabit, 10 Gigabit, and 40 Gigabit Ethernet
• Supports clock generation for IEEE-1588 applications
MAIN FEATURES
• Provides an integrated solution for Synchronous Equipment Timing
Source, including Stratum 3, SMC, EEC-Option 1 and EEC-
Option 2 Clocks
• Integrates T4 DPLL and T0 DPLL; T4 DPLL locks independently or
locks to T0 DPLL
• Supports programmable DPLL bandwidth (0.5 mHz to 35 Hz) and
damping factor (1.2 to 20 in 5 steps)
• Supports 1.1X10-5 ppm absolute holdover accuracy and
4.4X10-8 ppm instantaneous holdover accuracy
• Supports hitless reference switching to minimize phase transients
on T0 DPLL output to be no more than 0.61 ns
• Integrates 2 jitter attenuating APLLs to generate ultra-low jitter
clocks
Supports 3 clock modes: SONET, Ethernet, and Ethernet LAN-
PHY
Supports up to two crystal connections, allowing each APLL to
support up to two modes of operation
• Supports input and output clocks whose frequencies range from
1PPS to 644.53125 MHz
Includes 1PPS clock input and output
Provides IN1 and IN2 for 64 kHz + 8 kHz or
64 kHz + 8 kHz + 0.4 kHz composite clocks
Provides IN3, IN4, IN7~IN14 input CMOS clocks whose frequen-
cies range from 1PPS to 156.25 MHz
Provides IN5 and IN6 input differential clocks whose frequencies
range from 1PPS to 625 MHz
Provides OUT1 to OUT5 output CMOS clocks whose frequency
cover from 1PPS to 125 MHz
Provides OUT6,OUT7,OUT10 and OUT11 output differential
clocks whose frequency cover from 25 MHz to 644.53125 MHz
Provides OUT8 for composite clocks and OUT9 for 1.544 MHz/
2.048 MHz (BITS/SSU)
• Provides output clocks for BITS, GPS, 3G, GSM, etc.
• Provides a 1PPS, 2 kHz, 4 kHz, or 8 kHz frame sync input signal,
and a 1PPS, 2 kHz or 8 kHz frame sync output signal
• Internal DCO can be controlled by an external processor to be used
for IEEE-1588 clock generation
• Supports programmable input-to-output phase offset adjustment
• Limits the phase and frequency offset of the outputs
• Supports Forced or Automatic operating mode switch controlled by
an internal state machine. Automatic mode switch supports Free-
Run, Locked and Holdover modes
• Supports manual and automatic selected input clock switch
• Supports automatic hitless selected input clock switch on clock fail-
ure
• Supports three types of input clock sources: recovered clock from
STM-N or OC-n, PDH network synchronization timing and external
synchronization reference timing
• Supports AMI, LVPECL/LVDS and CMOS input/output technologies
• Supports Master/Slave application (two chips used together) to
enable system protection against single chip failure
• Supports Telcordia GR-1244-CORE, Telcordia GR-253-CORE,
ITU-T G.812, ITU-T G.8262, ITU-T G.813 and ITU-T G.783 Recom-
mendations
OTHER FEATURES
• I2C Microprocessor interface
• IEEE 1149.1 JTAG Boundary Scan
• Single 3.3 V operation with 5 V tolerant CMOS I/Os
• 1mm ball pitch CABGA green package
APPLICATIONS
• SMC / SEC (SONET / SDH equipment)
• EEC (Synchronous Ethernet equipment)
• Core and access IP switches / routers
• Gigabit and Terabit IP switches / routers
• Cellular and WLL base-station node clocks
• Broadband and multi-service access equipment
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
2013 Integrated Device Technology, Inc.
1
July 1, 2013
DSC-7238/-




IDT82V3910 pdf, 반도체, 판매, 대치품
IDT82V3910 SHORT FORM DATASHEET
SYNCHRONOUS ETHERNET SETS FOR 10GBE AND 40GBE
1 PIN ASSIGNMENT
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
IC10
VDDA
XTAL1_IN
CAP1
IN_APLL1_N
EG
OUT8_NEG
IN1
TDI
IC7
FF_SRCSW
OSCI
TMS
IC6
TRST
A
B
IC11
IN_APLL1_P
TDO/ 
VSSA XTAL1_OUT VSSAO
OS OUT8_POS IN2 T0_LOS_lNT VSSAO
TCK
VSSA
VSSA
VSSDO
VDDDO
B
C
MFRSYNC_2 FRSYNC_8K_
IC4 VDDA
NC
CAP2
K_1PPS
1PPS
VDDDO
VSSDO
VDDA
VSSA
VDDA
VDDA
INT_REQ
OUT9
C
D
VSSA
VSSAO
CAP3
VSSA
VDDA
MS/SL
VSSD
VDDD
IC2
VDDA
VSSA
VDDA
OUT4
OUT5
D
E XTAL3_IN XTAL3_OUT VSSA VSSAO VSSA SONET/SDH VSSD VDDD
IC1
VSSA
VDDA
VSSA
OUT2
OUT3
E
F
VDDD
VSSD
VSSAO
VSSA
VDDA
VSSAO
VSSD
VDDD
VSSD
VDDD EX_SYNC1 VDDDO
OUT1
VSSDO
F
G
VSSD
VDDD
VSSAO
VSSAO
VSSAO
VSSD
VDDD
IC3
VDDD
VSSD
EX_SYNC2
IN12
IN11
IN13
G
H
VDDAO
VSSAO
VDDAO
VSSAO
VSSAO
VSSAO
VSSD
VDDD
VSSD
VDDD
IN10
IN14
RST
IN3
H
J
OUT6_NEG OUT6_POS VDDAO
VSSAO
VDDAO
VSSAO
VDDAO
VSSAO
VSSA
VDDA
T0_LOCK
IN9
IN4
IN7
J
K
VSSAO
VSSAO
VSSAO
VDDAO
VSSAO
VDDAO
VSSAO
VSSD
VDDD
VSSAO T4_LOCK
IN8
I2C_SCL I2C_SDA
K
L
OUT7_NEG OUT7_POS VDDAO
VSSAO
VSSAO
VSSAO
VSSAO I2C_AD1 I2C_AD2
CAP4
VSSA
CAP5
VSSA
CAP6
L
M
VDDAO
VSSAO
VSSAO
VSSAO
VDDAO
VSSAO
VDDAO
VSSAO
VSSAO
VSSAO
VSSAO
NC XTAL4_OUT XTAL4_IN
M
N
VSSAO
OUT10_POS
VSSAO
OUT11_POS
VSSAO
IN_APLL2_P
OS IN5_POS
IN6_POS
VSSA XTAL2_OUT VSSA
P
VDDAO OUT10_NEG
VSSAO
IN_APLL2_N
OUT11_NEG VDDAO EG IN5_NEG
IN6_NEG
VDDA
XTAL2_IN VDDA
1 2 3 4 5 6 7 8 9 10 11
Key:
Diff 
Outputs
Outputs
Inputs
Power Ground
IC9
VSSAO
VSSA
IC8 IC5 VDDA
12 13 14
N
P
Figure 2. Pin Assignment (Top View)
Pin Assignment
4
July 1, 2013

4페이지










IDT82V3910 전자부품, 판매, 대치품
IDT82V3910 SHORT FORM DATASHEET
SYNCHRONOUS ETHERNET SETS FOR 10GBE AND 40GBE
Table 1: Pin Description (Continued)
Name
Pin No.
I/O
IN14 H12
IN_APLL1_POS
IN_APLL1_NEG
IN_APLL2_POS
IN_APLL2_NEG
B5
A5
N6
P6
FRSYN-
C_8K_1PPS
MFRSYN-
C_2K_1PPS
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6_POS
OUT6_NEG
C6
C5
F13
E13
E14
D13
D14
J2
J1
I pull-down
I pull-down
I pull-up/
pull-down
I pull-down
I pull-up/
pull-down
O
O
O
O
OUT7_POS
OUT7_NEG
OUT8_POS
OUT8_NEG
OUT9
OUT10_POS
OUT10_NEG
L2
L1
B6
A6
C14
N2
P2
O
O
O
O
OUT11_POS
OUT11_NEG
N4
P4
O
CAP1, CAP2,
CAP3
A4, C4, D3
O
Type Description 1
CMOS
IN14: Input Clock 14
A 1 PPS, 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz,
6.48 MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
155.52 MHz or 156.25 MHz clock is input on this pin.
LVPECL/LVDS/
LVHSTL/SSTL/
HCSL
IN_APLL1_POS / IN_APLL1_NEG: Input Clock to APLL1
Direct input clock to APLL1. This pin is used for test. It can be left floating or a 1kresistor
can be tied from IN_APLL1_POS to ground.
LVPECL/LVDS/
LVHSTL/SSTL/
HCSL
IN_APLL2_POS / IN_APLL2_NEG: Input Clock APLL2
Direct input clock to APLL2. This pin is used for test. It can be left floating or a 1kresistor
can be tied from IN_APLL2_POS to ground.
Output Frame Synchronization Signal
CMOS
FRSYNC_8K_1PPS: 8 kHz Frame Sync Output
An 8 kHz signal or a 1PPS Frame Pulse is output on this pin.
CMOS
MFRSYNC_2K_1PPS: 2 kHz Multiframe Sync Output
A 2 kHz signal or a 1PPS Frame Pulse is output on this pin.
Output Clock
CMOS
OUT1 ~ OUT5: Output Clock 1 ~ 5
A 1 pps, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz, 25MHz, or 125 MHz clock is output on these pins.
OUT6_POS / OUT6_NEG: Positive / Negative Output Clock 6
A SONET based (77.76 MHz, 155.52 MHz, 311.04 MHz, 622.08 MHz), Ethernet based (25
LVPECL/LVDS MHz, 125 MHz, 156.25 MHz, 312.5 MHz, 625 MHz), or Ethernet LAN based (161.1328125
MHz, 322.265625 MHz, 644.53125 MHz) clock is differentially output on this pair of pins from
APLL1.
OUT7_POS / OUT7_NEG: Positive / Negative Output Clock 7
A SONET based (77.76 MHz, 155.52 MHz, 311.04 MHz, 622.08 MHz), Ethernet based (25
LVPECL/LVDS MHz, 125 MHz, 156.25 MHz, 312.5 MHz, 625 MHz), or Ethernet LAN based (161.1328125
MHz, 322.265625 MHz, 644.53125 MHz) clock is differentially output on this pair of pins from
APLL1.
OUT8_POS / OUT8_NEG: Positive / Negative Output Clock 8
AMI A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is differentially output on this
pair of pins.
CMOS
OUT9: Output Clock 9
A 1.544 MHz (SONET) / 2.048 MHz (SDH) BITS/SSU clock is output on this pin.
OUT10_POS / OUT10_NEG: Positive / Negative Output Clock 10
A SONET based (77.76 MHz, 155.52 MHz, 311.04 MHz, 622.08 MHz), Ethernet based (25
LVPECL/LVDS MHz, 125 MHz, 156.25 MHz, 312.5 MHz, 625 MHz), or Ethernet LAN based (161.1328125
MHz, 322.265625 MHz, 644.53125 MHz) clock is differentially output on this pair of pins from
APLL2.
OUT11_POS / OUT11_NEG: Positive / Negative Output Clock 11
A SONET based (77.76 MHz, 155.52 MHz, 311.04 MHz, 622.08 MHz), Ethernet based (25
LVPECL/LVDS MHz, 125 MHz, 156.25 MHz, 312.5 MHz, 625 MHz), or Ethernet LAN based (161.1328125
MHz, 322.265625 MHz, 644.53125 MHz) clock is differentially output on this pair of pins from
APLL2.
Miscellaneous
Analog
CAP1, CAP2 and CAP3: Analog Power Filter Capacitor connection 1 to 3
Connect a 10uF capacitor in parallel with a low ESR 100nF capacitor between these pins
and VSS1
Pin Description
7
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IDT82V3910

Synchronous Ethernet SETS

Integrated Device Technology
Integrated Device Technology

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