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PDF IDT8T39S10I Data sheet ( Hoja de datos )
| Número de pieza | IDT8T39S10I | |
| Descripción | Crystal or Differential to Differential Clock Fanout Buffer | |
| Fabricantes | Integrated Device Technology | |
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Crystal or Differential to Differential
Clock Fanout Buffer
IDT8T39S10I
DATASHEET
General Description
The IDT8T39S10I is a high-performance clock fanout buffer. The
input clock can be selected from two differential inputs or one crystal
input. The internal oscillator circuit is automatically disabled if the
crystal input is not selected. The crystal pin can be driven by
single-ended clock when crystal is bypassed.The selected signal is
distributed to ten differential outputs which can be configured as
LVPECL, LVDS or HSCL outputs. In addition, an LVCMOS output is
provided. All outputs can be disabled into a high-impedance state.
The device is designed for signal fanout of high-frequency, low
phase-noise clock and data signal. The outputs are at a defined level
when inputs are open circuit or tied to ground. It is designed to
operate from a 3.3V or 2.5V core power supply, and either a 3.3V or
2.5V output operating supply.
Features
• Two differential reference clock input pairs
• Differential input pairs can accept the following differential input
levels: LVPECL, LVDS, HCSL
• Crystal Oscillator Interface
• Crystal input frequency range: 10MHz to 40MHz
• Maximum Output Frequency
LVPECL - 2GHz
LVDS - 2GHz
HCSL - 250MHz
LVCMOS - 250MHz
• Two banks, each has five differential output pairs that can be
configured as LVPECL or LVDS or HCSL
• One single-ended reference output with synchronous enable to
avoid clock glitch
• Output skew: (Bank A and Bank B at the same output level)
70ps (max)
• Part-to-part skew: 250ps (max)
• Additive RMS phase jitter: 0.153ps (typical)
• Supply voltage modes:
VDD/VDDO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
IDT8T39S10NLGI REVISION A MARCH 18. 2014
1
©2014 Integrated Device Technology, Inc.
1 page  
IDT8T39S10I Data Sheet
CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER
Table 3D. Input/Output Operation Table, SMODEA
Input Status
SMODEA[1:0]
11
00, 01 or 10
REF_SEL[1:0]
Don’t care
10 or 11
CLKx and nCLKx
Don’t Care
Don’t Care
CLK0 and nCLK0 are both open circuit
00, 01 or 10
00 (default)
CLK0 and nCLK0 are tied to ground
CLK0 is high, nCLK0 is low
CLK0 is low, nCLK0 is high
CLK1 and nCLK1 are both open circuit
00, 01 or 10
01
CLK1 and CLK1 are tied to ground.
CLK1 is high, nCLK1 is low
CLK1 is low, nCLK1 is high
Output State
QA[4:0], nQA[4:0]
High Impedance
Fanout crystal oscillator
QA[4:0] = Low
nQA4:0] = High
QA[4:0] = Low
nQA[4:0] = High
QA[4:0] = High
nQA[4:0] = Low
QA[4:0] = Low
nQA[4:0] = High
QA[4:0] = Low
nQA4:0] = High
QA[4:0] = Low
nQA[4:0] = High
QA[4:0] = High
nQA[4:0] = Low
QA[4:0] = Low
nQA4:0]=High
Table 3E. Input/Output Operation Table, SMODEB
Input Status
SMODEB[1:0]
11
00, 01 or 10
REF_SEL[1:0]
Don’t care
10 or 11
CLKx and nCLKx
Don’t Care
Don’t Care
CLK0 and nCLK0 are both open circuit
00, 01 or 10
00 (default)
CLK0 and nCLK0 are tied to ground
CLK0 is high, nCLK0 is low
CLK0 is low, nCLK0 is high
CLK1 and nCLK1 are both open circuit
00, 01 or 10
01
CLK1 and nCLK1 are tied to ground
CLK1 is high, nCLK1 is low
CLK1 is low, nCLK1 is high
Output State
QB[4:0], nQB[4:0]
High Impedance
Fanout crystal oscillator
QB[4:0] = Low
nQB4:0] = High
QB[4:0] = Low
nQB[4:0] = High
QB[4:0] = High
nQB[4:0] = Low
QB[4:0] = Low
nQB[4:0] = High
QB[4:0] = Low
nQB[4:0] = High
QB[4:0] = Low
nQB[4:0] = High
QB[4:0] = High
nQB[4:0] = Low
QB[4:0] = Low
nQB[4:0] = High
IDT8T39S10NLGI REVISION A MARCH 18. 2014
5
©2013 Integrated Device Technology, Inc.
5 Page 
IDT8T39S10I Data Sheet
CRYSTAL OR DIFFERENTIAL-TO-DIFFERENTIAL CLOCK FANOUT BUFFER
NOTE 6: TSTABLE is the time the differential clock must maintain a minimum ± 150mV differential voltage after rising/falling edges before it is
allowed to drop back into the VRB ±100mV differential range.
NOTE 7: Measurement taken from single-ended waveform.
NOTE 8: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 9: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 10: Measured at crosspoint where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.
NOTE 11: Refers to the total variation from the lowest crosspoint to the highest, regardless of which edge is crossing. Refers to all crosspoint
for this measurement.
NOTE 12: Defined as the total variation of all crossing voltages of rising Qx and falling nQx, This is the maximum allowed variance in Vcross
for any particular system.
NOTE 13: Measured from -150mV to +150mV on the differential waveform (Qx minus nQx). The signal must be monotonic through the
measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
Table 6B. AC Characteristics, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
Using External Crystal
10
40 MHz
fOUT
Output Frequency
LVDS, LVPECL
Outputs
HCSL Outputs
2000
250
MHz
MHz
LVCMOS Output
250 MHz
Additive Phase Jitter: 156.25MHz
SMODEA/B[1:0] = 00
tjit
Integration Range: 12kHz - 20MHz
SMODEA/B[1:0] = 01
REF_SEL[1:0] = 00 or 10
SMODEA/B[1:0] = 10
0.181
0.181
0.200
0.235
0.235
0.250
ps
ps
ps
tjit(Ø)
RMS Phase Jitter; 25MHz
Integration Range: 100Hz - 1MHz
REF_SEL[1:0] = 10 or 11
0.258
0.525
ps
Propagation Delay; CLK0, nCLK0 or
SMODEA/B[1:0] = 00
0.40
tPD
CLK1, nCLK1 to any Qx, nQx Outputs;
SMODEA/B[1:0] = 01
0.57
NOTE 1
SMODEA/B[1:0] = 10
1.75
1.60 ns
1.10 ns
2.85 ns
tsk(o)
Output Skew; NOTE 2, 3
70 ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
250 ps
VRB
Ring-back Voltage
Margin; NOTE 5, 6
HCSL Outputs
-100
100 mV
VMAX
Voltage High;
NOTE 7, 8
HCSL Outputs
920 mV
VMIN
Voltage Low;
NOTE 7, 9
HCSL Outputs
-150
+150
mV
VCROSS
Absolute Crossing
Voltage;
NOTE 7, 10, 11
HCSL Outputs
250 520 mV
VCROSS
Total Variation of
VCROSS over all edges; HCSL Outputs
NOTE 7, 10, 12
140 mV
Rise/Fall Edge Rate;
NOTE 13
HCSL Outputs
Measured between
150mV to +150mV
0.6
4.0 V/ns
tR / tF
Output Rise/Fall Time
SMODEA/B[1:0] = 00;
20% to 80%
60
200 310 ps
SMODEA/B[1:0] = 01;
20% to 80%
40
170 300 ps
MUX_ISOLATION MUX Isolation
156.25MHz
70 dB
Notes continued on next page.
IDT8T39S10NLGI REVISION A MARCH 18. 2014
11
©2013 Integrated Device Technology, Inc.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IDT8T39S10I.PDF ] | |
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