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ISL26104 데이터시트 PDF




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부품번호 ISL26104 기능
기능 Low-Noise 24-bit Delta Sigma ADC
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ISL26104 데이터시트, 핀배열, 회로
Low-Noise 24-bit Delta Sigma ADC
ISL26102, ISL26104
The ISL26102 and ISL26104 provide a low-noise
programmable gain amplifier along with a 24-bit Delta-Sigma
Analog-to-Digital Converter with two channel (ISL26102) or
four channel (ISL26104) differential, multiplexed inputs. The
devices feature exceptional noise performance for conversion
rates ranging from 2.5Sps to 4kSps.
The on-chip low-noise programmable-gain amplifier provides
gains ranging from 1 to 128, which supports ±19.5mVFS from
a 5V reference. The high input impedance allows direct
connection of sensors such as load cell bridges to ensure the
specified measurement accuracy without additional circuitry.
The Delta-Sigma ADC features a 3rd-order modulator providing
up to 21.5 bit noise-free performance (10Sps), with
user-selectable word rates. The converter can be operated
from an external clock source, an external crystal (typically
4.9152MHz), or the on-chip oscillator.
The ISL26102 and ISL26104 offer a simple-to-use serial
interface.
The ISL26102 and ISL26104 are available in a Thin Shrink
Small Outline Package (TSSOP). The devices are specified for
operation over the automotive temperature range (-40°C to
+105°C).
Features
• Programmable gain amplifier with gains of 1 to 128
• Low noise: 7nV/Hz @ PGA = 128
• Linearity error: 0.0002% FS
• Output word rates up to 4kSps
• Low-side switch for load cell power management
• +5V analog and +2.7V to +5V digital supplies
• ISL26102 in 24 Ld TSSOP
• ISL26104 in 28 Ld TSSOP
• ESD 7.5kV - HBM
Applications
• Weigh scales
• Temperature monitors and controls
• Load safety systems
• Industrial process control
• Pressure sensors
Related Literature
AN1704, “Precision Signal Path Data Acquisition System”
AVDD
ON-CHIP
TEMP
SENSOR
CAP
DVDD
DVDD
INTERNAL
CLOCK
EXTERNAL
OSCILLATOR
XTALIN/
CLOCK
XTALOUT
AIN1+
AIN1-
AIN2+
AIN2-
AIN3+
ISL26104 AIN3-
ONLY AIN4+
AIN4-
LSPS
INPUT
MULTIPLEXER
PGA
1, 2, 4, 8,16,
32, 64, 128
ΔΣ
ADC
CS
SDO/RDY
SDI
SCLK
PWDN
AGND
CAP DGND DGND VREF+ VREF- DGND DGND
FIGURE 1. BLOCK DIAGRAM
October 12, 2012
FN7608.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.




ISL26104 pdf, 반도체, 판매, 대치품
ISL26102, ISL26104
Absolute Maximum Ratings
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Analog In to AGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to AVDD+0.3V
Digital In to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to DVDD+0.3V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . . . . . . . . . .7.5kV
Machine Model (Per JESD22-A115). . . . . . . . . . . . . . . . . . . . . . . . . . 450V
Charged Device Model (Per JESD22-C101) . . . . . . . . . . . . . . . . . . . . . . 2000V
Input Current
Momentary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Latch-up
(Per JEDEC, JESD-78C; Class 2, Level A). . . .100mA @ +25°C and +105°C
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
24 Ld TSSOP Package (Notes 4, 5) . . . . . .
65
18
28 Ld TSSOP Package (Notes 4, 5) . . . . . .
63
18
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V to +5.25V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V to +5.25V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications VREF+ = 5.0V, VREF- = 0V, AVDD = 5V, DVDD = 5V XTALIN/CLOCK = 4.9152MHz (Note 6)
TA = -40°C to +105°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +105°C.
SYMBOL
PARAMETER
TEST LEVEL OR NOTES
MIN MAX
(Note 7) TYP (Note 7)
ANALOG INPUTS
VIN Differential Input Voltage Range
±0.5VREF/
Gain
Input Voltage Range: Common Mode +
Signal
Input Bias Current; AIN+, AIN-
Gain = 1
Gain = 2, 4, 8, 16, 32, 64, 128
Gain = 1
AGND + 0.1
AVDD - 0.1
AGND + 1.5
AVDD - 1.5
300
Gain = 2, 4, 8, 16, 32, 64, 128
3
Input Offset Current; AIN+, AIN-
Gain = 1
±20
Gain = 2, 4, 8, 16, 32, 64, 128
±1
SYSTEM PERFORMANCE
Resolution
No Missing Codes
24
INL Integral Nonlinearity
Gain = 1
±0.0002
±0.001
Gain = 2 to 128
±0.0004
Offset
Gain = 1
±0.4
Offset Drift
Full Scale Error
Full Scale Drift
CMRR Common Mode Rejection Ratio
PSRR Power Supply Rejection Ratio
OWR Output Word Rate (Note 8)
Gain = 1
Gain = 2 to 128
Gain = 1
Gain = 2 to 128
Gain = 1
Gain = 64
Gain = 128
Gain of 1
Gain of 128
Gain of 1
Gain of 128
±300
±300/Gain
± 10
±0.007
±0.02
±0.1
±3.5
±3.5
85 110
130
100
100 125
2.5 4000
UNITS
V
V
V
nA
nA
nA
nA
Bits
% FSR
% FSR
ppm of
FS
nV/°C
nV/°C
%
%
ppm/°C
ppm/°C
ppm/°C
dB
dB
dB
dB
SPS
4 FN7608.0
October 12, 2012

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ISL26104 전자부품, 판매, 대치품
ISL26102, ISL26104
TABLE 2. NOISE FREE BITS
OUTPUT WORD RATE
(Note 11)
NOISE-FREE BITS
1 2 4 8 16 32 64 128
2.5
21.9
21.8
21.8
21.9
21.6
21.4
20.8
19.8
5
21.8
21.7
21.7
21.7
21.5
21.1
20.4
19.5
10
21.5
21.4
21.5
21.3
21.2
20.7
19.9
19.0
20
21.2
21.2
21.2
21.0
20.9
20.3
19.5
18.6
40
20.8
20.8
20.8
20.6
20.4
19.8
19.0
18.0
80
20.4
20.4
20.4
20.2
19.9
19.4
18.5
17.6
100
20.3
20.3
20.2
20.0
19.8
19.2
18.4
17.4
160
19.9
20.0
19.8
19.7
19.4
18.8
18.0
17.0
200 19.8 19.8 19.7 19.6 19.3 18.7 17.8 16.9
320 19.5 19.5 19.3 19.3 19.0 18.3 17.5 16.5
400 19.3 19.3 19.2 19.1 18.8 18.1 17.3 16.4
640 19.0 18.9 18.9 18.8 18.5 17.8 17.0 16.0
800 18.8 18.8 18.7 18.6 18.4 17.7 16.8 15.9
1000
18.7 18.6 18.6 18.4 18.2 17.5 16.7 15.7
1280
18.5 18.4 18.4 18.3 18.0 17.3 16.5 15.5
1600
18.3 18.2 18.2 18.1 17.8 17.1 16.4 15.5
2000
18.2 18.1 18.0 18.0 17.7 17.0 16.3 15.3
2560
18.0
17.9
17.9
17.8
17.5
16.8
16.2
15.2
3200
17.8
17.8
17.7
17.6
17.3
16.7
16.0
15.1
4000
17.6
17.6
17.6
17.4
17.2
16.6
15.9
14.9
NOTE:
11. Noise-free resolution in Table 2 is calculated as LOG ((Input Span)/(RMS Noise x 6.6))/LOG(2). The result is rounded to the nearest tenth of a bit. The
Input Span is equivalent to ±0.5VREF/GAIN, VREF = 5V. The RMS noise is selected from Table 1 for the desired Output Word Rate and Gain option.
10 10000
8 NORMAL MODE
6
4
2
1000
100
10
NORMAL MODE, ALL PGA GAINS
POWERDOWN MODE
0
-40 -10 20 50 80 110
TEMPERATURE (°C)
FIGURE 3. ANALOG CURRENT vs TEMPERATURE (GAIN = 2 TO 128)
1
-40 -10 20 50 80
TEMPERATURE (°C)
FIGURE 4. DIGITAL CURRENT vs TEMPERATURE
110
7 FN7608.0
October 12, 2012

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관련 데이터시트

부품번호상세설명 및 기능제조사
ISL26102

Low-Noise 24-bit Delta Sigma ADC

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Intersil
ISL26104

Low-Noise 24-bit Delta Sigma ADC

Intersil
Intersil

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