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PDF SQS850EN Data sheet ( Hoja de datos )

Número de pieza SQS850EN
Descripción Automotive N-Channel MOSFET
Fabricantes Vishay 
Logotipo Vishay Logotipo



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No Preview Available ! SQS850EN Hoja de datos, Descripción, Manual

www.vishay.com
SQS850EN
Vishay Siliconix
Automotive N-Channel 60 V (D-S) 175 °C MOSFET
PRODUCT SUMMARY
VDS (V)
RDS(on) (Ω) at VGS = 10 V
RDS(on) (Ω) at VGS = 4.5 V
ID (A)
Configuration
60
0.0215
0.0261
12
Single
PowerPAK® 1212-8 Single
D
D8
D7
D6
5
FEATURES
• TrenchFET® power MOSFET
• AEC-Q101 qualified
• 100 % Rg and UIS tested
• Material categorization:
for definitions of compliance please see
www.vishay.com/doc?99912
D
3.3 mm
1
Top View
3.3 mm
Marking Code: Q019
ORDERING INFORMATION
Package
Lead (Pb)-free and Halogen-free
1
2S
3S
4S
G
Bottom View
G
N-Channel MOSFET
S
PowerPAK 1212-8
SQS850EN-T1-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current a
Continuous Source Current (Diode Conduction) a
Pulsed Drain Current b
Single Pulse Avalanche Current
Single Pulse Avalanche Energy
Maximum Power Dissipation b
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature) d, e
TC = 25 °C
TC = 125 °C
L = 0.1 mH
TC = 25 °C
TC = 125 °C
VDS
VGS
ID
IS
IDM
IAS
EAS
PD
TJ, Tstg
LIMIT
60
± 20
12
12
12
48
23
26
33
11
-55 to +175
260
UNIT
V
A
mJ
W
°C
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
LIMIT
UNIT
Junction-to-Ambient
Junction-to-Case (Drain)
PCB Mount c
RthJA
81
°C/W
RthJC
4.5
Notes
a. Package limited.
b. Pulse test; pulse width 300 μs, duty cycle 2 %.
c. When mounted on 1" square PCB (FR4 material).
d. See solder profile (www.vishay.com/doc?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed
and is not required to ensure adequate bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
S14-2054-Rev. B, 20-Oct-14
1
Document Number: 62855
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

1 page




SQS850EN pdf
www.vishay.com
THERMAL RATINGS (TA = 25 °C, unless otherwise noted)
100
IDM Limited
10 Limited by RDS(on)*
1
ID Limited
SQS850EN
Vishay Siliconix
100 μs
1 ms
10 ms
100 ms, 1 s, 10 s, DC
1
Duty Cycle = 0.5
0.1
TC = 25 °C
Single Pulse
BVDSS Limited
0.01
0.01 0.1 1 10 100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10-4
10-3
Notes:
PDM
10-2
10-1
1
Square Wave Pulse Duration (s)
t1
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = RthJA = 81 °C/W
3. TJM - TA = PDMZthJA(t)
4. Surface Mounted
10 100 1000
Normalized Thermal Transient Impedance, Junction-to-Ambient
S14-2054-Rev. B, 20-Oct-14
5
Document Number: 62855
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

5 Page





SQS850EN arduino
AN822
Vishay Siliconix
TABLE 1: EQIVALENT STEADY STATE PERFORMANCE
Package
Configuration
SO-8
Single Dual
TSSOP-8
Single Dual
TSOP-8
Single Dual
Thermal Resiatance RthJC(C/W) 20 40 52 83 40 90
PPAK 1212
Single Dual
2.4 5.5
PPAK SO-8
Single Dual
1.8 5.5
PowerPAK 1212
49.8 °C
Standard SO-8
85 °C
Standard TSSOP-8
149 °C
TSOP-6
125 °C
2.4 °C/W
PC Board at 45 °C
20 °C/W
52 °C/W
Figure 4. Temperature of Devices on a PC Board
40 °C/W
THERMAL PERFORMANCE
Introduction
Spreading Copper
A basic measure of a device’s thermal performance is
the junction-to-case thermal resistance, Rθjc, or the
junction to- foot thermal resistance, Rθjf. This parameter
is measured for the device mounted to an infinite heat
sink and is therefore a characterization of the device
only, in other words, independent of the properties of the
object to which the device is mounted. Table 1 shows a
comparison of the PowerPAK 1212-8, PowerPAK SO-8,
standard TSSOP-8 and SO-8 equivalent steady state
performance.
By minimizing the junction-to-foot thermal resistance, the
MOSFET die temperature is very close to the tempera-
ture of the PC board. Consider four devices mounted on
a PC board with a board temperature of 45 °C (Figure 4).
Suppose each device is dissipating 2 W. Using the junc-
tion-to-foot thermal resistance characteristics of the
PowerPAK 1212-8 and the other SMT packages, die
temperatures are determined to be 49.8 °C for the Pow-
erPAK 1212-8, 85 °C for the standard SO-8, 149 °C for
standard TSSOP-8, and 125 °C for TSOP-6. This is a
4.8 °C rise above the board temperature for the Power-
PAK 1212-8, and over 40 °C for other SMT packages. A
4.8 °C rise has minimal effect on rDS(ON) whereas a rise
of over 40 °C will cause an increase in rDS(ON) as high
as 20 %.
Designers add additional copper, spreading copper, to
the drain pad to aid in conducting heat from a device. It
is helpful to have some information about the thermal
performance for a given area of spreading copper.
Figure 5 and Figure 6 show the thermal resistance of a
PowerPAK 1212-8 single and dual devices mounted on
a 2-in. x 2-in., four-layer FR-4 PC boards. The two inter-
nal layers and the backside layer are solid copper. The
internal layers were chosen as solid copper to model the
large power and ground planes common in many appli-
cations. The top layer was cut back to a smaller area and
at each step junction-to-ambient thermal resistance
measurements were taken. The results indicate that an
area above 0.2 to 0.3 square inches of spreading copper
gives no additional thermal performance improvement.
A subsequent experiment was run where the copper on
the back-side was reduced, first to 50 % in stripes to
mimic circuit traces, and then totally removed. No signif-
icant effect was observed.
Document Number 71681
03-Mar-06
www.vishay.com
3

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