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PDF SQ7414AEN Data sheet ( Hoja de datos )
| Número de pieza | SQ7414AEN | |
| Descripción | Automotive N-Channel MOSFET | |
| Fabricantes | Vishay | |
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SQ7414AEN
Vishay Siliconix
Automotive N-Channel 60 V (D-S) 175 °C MOSFET
PRODUCT SUMMARY
VDS (V)
RDS(on) (Ω) at VGS = 10 V
RDS(on) (Ω) at VGS = 4.5 V
ID (A)
Configuration
Package
60
0.026
0.036
16
Single
PowerPAK 1212-8
PowerPAK® 1212-8 Single
D
D8
D7
D6
5
FEATURES
• TrenchFET® power MOSFET
• Low thermal resistance PowerPAK® 1212-8
package with 1.07 mm profile
• PWM optimized
• 100 % Rg and UIS tested
• AEC-Q101 qualified
• Material categorization: for definitions of
compliance please see www.vishay.com/doc?99912
D
3.3 mm
1
Top View
3.3 mm
Marking Code: Q013
1
2S
3S
4S
G
Bottom View
G
N-Channel MOSFET
S
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current a
Continuous Source Current (Diode Conduction) a
Pulsed Drain Current b
Single Pulse Avalanche Current
Single Pulse Avalanche Energy
Maximum Power Dissipation b
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature) d, e
TC = 25 °C
TC = 125 °C
L = 0.1 mH
TC = 25 °C
TC = 125 °C
VDS
VGS
ID
IS
IDM
IAS
EAS
PD
TJ, Tstg
LIMIT
60
± 20
16
16
16
72
18
16
62
20
-55 to +175
260
UNIT
V
A
mJ
W
°C
THERMAL RESISTANCE RATINGS
PARAMETER
Junction-to-Ambient
Junction-to-Case (Drain)
PCB Mount c
SYMBOL
RthJA
RthJC
LIMIT
81
2.4
UNIT
°C/W
Notes
a. Package limited.
b. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.
c. When mounted on 1" square PCB (FR4 material).
d. See solder profile (www.vishay.com/doc?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed
and is not required to ensure adequate bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
S15-1878-Rev. C, 17-Aug-15
1
Document Number: 67050
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
1 page  
www.vishay.com
THERMAL RATINGS (TA = 25 °C, unless otherwise noted)
100
10 IDM Limited
ID Limited
1
Limited by RDS(on)*
SQ7414AEN
Vishay Siliconix
100 μs
1 ms
10 ms
100 ms, 1 s, 10 s, DC
1
Duty Cycle = 0.5
0.1
TC = 25 °C
Single Pulse
BVDSS Limited
0.01
0.01
0.1
1
10
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area
100
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10-4
10-3
Notes:
PDM
t1
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = RthJA = 81 °C/W
3. TJM - TA = PDMZthJA(t)
4. Surface Mounted
10-2
10-1
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
100
1000
S15-1878-Rev. C, 17-Aug-15
5
Document Number: 67050
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
5 Page 
AN822
Vishay Siliconix
PowerPAK 1212 DUAL
To take the advantage of the dual PowerPAK 1212-8’s
thermal performance, the minimum recommended
land pattern can be found in Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 dual in the index of this doc-
ument.
The gap between the two drain pads is 10 mils. This
matches the spacing of the two drain pads on the Pow-
erPAK 1212-8 dual package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
area of about 0.3 to 0.5 in2 of will yield little improve-
ment in thermal performance.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder
reflow reliability requirements. Devices are subjected
to solder reflow as a preconditioning test and are then
reliability-tested using temperature cycle, bias humid-
ity, HAST, or pressure pot. The solder reflow tempera-
ture profile used, and the temperatures and time
duration, are shown in Figures 2 and 3. For the lead
(Pb)-free solder profile, see http://www.vishay.com/
doc?73257.
Ramp-Up Rate
Temperature at 155 ± 15 °C
Temperature Above 180 °C
Maximum Temperature
Time at Maximum Temperature
Ramp-Down Rate
+ 6 °C /Second Maximum
120 Seconds Maximum
70 - 180 Seconds
240 + 5/- 0 °C
20 - 40 Seconds
+ 6 °C/Second Maximum
Figure 2. Solder Reflow Temperature Profile
140 - 170 °C
3° C/s (max)
210 - 220 °C
3 ° C/s (max)
60 s (min)
Pre-Heating Zone
10 s (max)
183 °C
50 s (max)
Reflow Zone
Maximum peak temperature at 240 °C is allowed.
4 ° C/s (max)
www.vishay.com
2
Figure 3. Solder Reflow Temperatures and Time Durations
Document Number 71681
03-Mar-06
11 Page | ||
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