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부품번호 PCF8574A 기능
기능 Remote 8-bit I/O expander for I2C-bus
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PCF8574A 데이터시트, 핀배열, 회로
PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
Rev. 5 — 27 May 2013
Product data sheet
1. General description
The PCF8574/74A provides general-purpose remote I/O expansion via the two-wire
bidirectional I2C-bus (serial clock (SCL), serial data (SDA)).
The devices consist of eight quasi-bidirectional ports, 100 kHz I2C-bus interface, three
hardware address inputs and interrupt output operating between 2.5 V and 6 V. The
quasi-bidirectional port can be independently assigned as an input to monitor interrupt
status or keypads, or as an output to activate indicator devices such as LEDs. System
master can read from the input port or write to the output port through a single register.
The low current consumption of 2.5 A (typical, static) is great for mobile applications and
the latched output ports directly drive LEDs.
The PCF8574 and PCF8574A are identical, except for the different fixed portion of the
slave address. The three hardware address pins allow eight of each device to be on the
same I2C-bus, so there can be up to 16 of these I/O expanders PCF8574/74A together on
the same I2C-bus, supporting up to 128 I/Os (for example, 128 LEDs).
The active LOW open-drain interrupt output (INT) can be connected to the interrupt logic
of the microcontroller and is activated when any input state differs from its corresponding
input port register state. It is used to indicate to the microcontroller that an input state has
changed and the device needs to be interrogated without the microcontroller continuously
polling the input register via the I2C-bus.
The internal Power-On Reset (POR) initializes the I/Os as inputs with a weak internal
pull-up 100 A current source.
2. Features and benefits
I2C-bus to parallel port expander
100 kHz I2C-bus interface (Standard-mode I2C-bus)
Operating supply voltage 2.5 V to 6 V with non-overvoltage tolerant I/O held to VDD
with 100 A current source
8-bit remote I/O pins that default to inputs at power-up
Latched outputs directly drive LEDs
Total package sink capability of 80 mA
Active LOW open-drain interrupt output
Eight programmable slave addresses using three address pins
Low standby current (2.5 A typical)
40 C to +85 C operation
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101




PCF8574A pdf, 반도체, 판매, 대치품
NXP Semiconductors
6. Pinning information
6.1 Pinning
PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
A0 1
A1 2
16 VDD
15 SDA
A2 3
14 SCL
P0 4 PCF8574P 13 INT
P1 5 PCF8574AP 12 P7
P2 6
11 P6
P3 7
10 P5
VSS 8
9 P4
002aad625
A0 1
A1 2
A2 3
P0 4
P1 5
P2 6
P3 7
VSS 8
PCF8574T/3
PCF8574AT/3
16 VDD
15 SDA
14 SCL
13 INT
12 P7
11 P6
10 P5
9 P4
002aad626
INT 1
SCL 2
n.c. 3
SDA 4
VDD 5
A0 6
A1 7
n.c. 8
A2 9
P0 10
PCF8574TS/3
PCF8574ATS/3
20 P7
19 P6
18 n.c.
17 P5
16 P4
15 VSS
14 P3
13 n.c.
12 P2
11 P1
002aad627
Fig 3. Pin configuration for DIP16 Fig 4. Pin configuration for SO16 Fig 5. Pin configuration for
SSOP20
6.2 Pin description
Table 3.
Symbol
A0
A1
A2
P0
P1
P2
P3
VSS
P4
P5
P6
P7
INT
SCL
SDA
VDD
n.c.
Pin description
Pin
DIP16, SO16 SSOP20
16
27
39
4 10
5 11
6 12
7 14
8 15
9 16
10 17
11 19
12 20
13 1
14 2
15 4
16 5
- 3, 8, 13, 18
Description
address input 0
address input 1
address input 2
quasi-bidirectional I/O 0
quasi-bidirectional I/O 1
quasi-bidirectional I/O 2
quasi-bidirectional I/O 3
supply ground
quasi-bidirectional I/O 4
quasi-bidirectional I/O 5
quasi-bidirectional I/O 6
quasi-bidirectional I/O 7
interrupt output (active LOW)
serial clock line
serial data line
supply voltage
not connected
PCF8574_PCF8574A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 27 May 2013
© NXP B.V. 2013. All rights reserved.
4 of 33

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PCF8574A 전자부품, 판매, 대치품
NXP Semiconductors
PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
There is only one register to control four possibilities of the port pin: Input HIGH, input
LOW, output HIGH, or output LOW.
Input HIGH: The master needs to write 1 to the register to set the port as an input mode
if the device is not in the default power-on condition. The master reads the register to
check the input status. If the external source pulls the port pin up to VDD or drives
logic 1, then the master will read the value of 1.
Input LOW: The master needs to write 1 to the register to set the port to input mode if
the device is not in the default power-on condition. The master reads the register to
check the input status. If the external source pulls the port pin down to VSS or drives
logic 0, which sinks the weak 100 A current source, then the master will read the value
of 0.
Output HIGH: The master writes 1 to the register. There is an additional ‘accelerator’ or
strong pull-up current when the master sets the port HIGH. The additional strong pull-up
is only active during the HIGH time of the acknowledge clock cycle. This accelerator
current helps the port’s 100 A current source make a faster rising edge into a heavily
loaded output, but only at the start of the acknowledge clock cycle to avoid bus
contention if an external signal is pulling the port LOW to VSS/driving the port with
logic 0 at the same time. After the half clock cycle there is only the 100 A current
source to hold the port HIGH.
Output LOW: The master writes 0 to the register. There is a strong current sink
transistor that holds the port pin LOW. A large current may flow into the port, which
could potentially damage the part if the master writes a 0 to the register and an external
source is pulling the port HIGH at the same time.
input HIGH
pull-up with
resistor to VDD or
external drive HIGH
P port
P7 - P0
pull-down with
resistor to VSS or
external drive LOW
input LOW
Fig 7. Simple quasi-bidirectional I/O
VDD
weak 100 µA
current source
(inactive when
output LOW)
accelerator
pull-up
output HIGH
output LOW
VSS
002aah683
PCF8574_PCF8574A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 27 May 2013
© NXP B.V. 2013. All rights reserved.
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