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PDF CMX7261 Data sheet ( Hoja de datos )
| Número de pieza | CMX7261 | |
| Descripción | Multi-transcoder | |
| Fabricantes | Consumer Microcircuits Limited | |
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CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CMX7261
Multi-transcoder
D/7261_FI-1.x/9 March 2012
DATASHEET
Advance Information
7261 FI-1.x Multi-transcoder
Features
Half-duplex operation
Full-duplex operation
Multiple codec support:
o PCM (linear, µ-law, A-law), CVSD and
G.729A codecs
Multiple transcoding support:
o PCM to CVSD and reverse
o PCM to G.729A and reverse
o CVSD to G.729A and reverse
o PCM μ/A/linear to PCM μ/A/linear
transcoder
No external DSP or codecs required: simply
upload Function Image™ (FI)
Transcoder routing:
o Choice of input sources – C-BUS transfer
to host, external PCM device/codec,
analogue audio input
o Choice of output sources – C-BUS transfer
to host, external PCM device/codec,
analogue audio output
Voice activity detection
C-BUS host serial interface
o SPI-like with register addressing
o Read/Write 128-byte FIFOs and data buffers
to streamline transfers and relax host service
latency
Auxiliary functions
o Three GPIOs
o Analogue input/output gain adjustment
o Analogue input multiplexer
o Analogue output multiplexer
Master/Slave PCM serial interface
o For external audio CODEC
Low power 3.3V operation with powersave
functions
Small 64-pin VQFN/LQFP package
Applications
Half duplex digital radio systems
Full duplex digital radio systems
Personal area network voice links
Privacy-type digital voice communications
Wireless PBX
VoIP applications
Digital Software Defined Radio (SDR)
Analogue In
Analogue Out
External ADC /
DAC
GPIOs
ADC
Digital
Filters
DAC
Digital
Filters
PCM Talk-
Through /
PCM
CMX7261
Multi-transcoder
FIFO
Configuration
Transcoder
Function
Image™
3.3V
C-BUS
Host
µC
3.3V
This document contains:
Datasheet
User
Manual
2012 CML Microsystems Plc
1 page  
CMX7261 Voice Multi-transcoder
CMX7261
Figure 15 Basic C-BUS Transactions ........................................................................................... 24
Figure 16 C-BUS Data-Streaming Operation................................................................................ 25
Figure 17 FI Loading from Host .................................................................................................... 27
Figure 18 FI Loading from Serial Memory..................................................................................... 28
Figure 19 Block Diagram of Conceptual CELP Synthesis Model.................................................. 30
Figure 20 CVSD Encoder.............................................................................................................. 31
Figure 21 CVSD Decoder.............................................................................................................. 31
Figure 22 Audio Input and Audio Output FIFOs ............................................................................ 33
Figure 23 Input Data Transfer into the CMX7261 ......................................................................... 36
Figure 24 Output Data Transfer from the CMX7261..................................................................... 37
Figure 25 Examples of Sample Rate Conversion ......................................................................... 41
Figure 26 VAD Block Diagram ...................................................................................................... 42
Figure 27 Transcoder Operation Flowchart .................................................................................. 46
Figure 28 Full duplex Transcoder Operation Flowchart ................................................................ 49
Figure 29 CVSD 16kbps Frequency Response ............................................................................ 59
Figure 30 CVSD 32kbps Frequency Response ............................................................................ 59
Figure 31 C-BUS Timing ............................................................................................................... 60
Figure 32 PCM Internal Clock Timings ......................................................................................... 61
Figure 33 PCM External Clock Timings ........................................................................................ 62
Figure 34 Mechanical Outline of 64-pin VQFN (Q1) ..................................................................... 63
Figure 35 Mechanical Outline of 64-pin LQFP (L9)....................................................................... 63
Information in this data sheet should not be relied upon for final product design. It is always recommended
that you check for the latest product datasheet version from the CML website: [www.cmlmicro.com].
1.1 History
Version
9
8
7
6
5
4
Changes
Added availability of L9 package
Added analogue input multiplexer.
Updated analogue output multiplexer.
Added differential speaker driver output.
Added single ended analogue input.
Added independent coarse gain control for ANAOUT, MONOUT and SPKR.
Added Reg Done Select register to provide host handshake.
Added programming register to enable/disable GPIO bus-hold function.
Added programming register to enable/disable core voltage regulator.
Updated C-BUS Timing information to show C-BUS usage at 10MHz clock speed.
Advice in section 5.6 greyed out as not implemented in current FI.
Added advice about terminating unconnected GPIO pins in section 5.6
Updated G.729A current consumption figures, to reflect optimisations done on the
G.729A algorithm.
Documented the SSOUT0 pin which is used when booting from external serial
memory. This pin replaces GPIOD.
Removed the BOOTEN1,2 = 00 reset mechanism as it could be unreliable
Date
13/3/12
7/12/11
22/08/11
17/08/11
27/07/11
08/04/11
2012 CML Microsystems Plc
Page 5
D/7261_FI-1.x/9
5 Page 
CMX7261 Voice Multi-transcoder
CMX7261
64-pin
Q1/L9
Pin No.
Pin
Name
Type
45 DVDD3V3
PWR
46 NC
47 DVSS
48 DVSS
49 XTALN
NC
PWR
PWR
OP
50 XTAL/CLOCK IP
51 NC
52 NC
53 SCLK
NC
NC
IP
54 RDATA
TS OP
55 CDATA
56 CSN
IP
IP
57 IRQN
OP
58 DVCORE2
PWR
59 SDO
60 FSO
61 SDI
62 SSOUT0
63 CLKO
64 FSI
OP
OP
IP
OP
OP
BI
Signal Description
3.3V positive supply rail for the digital on-chip circuits. This
pin should be decoupled to DVSS by capacitors mounted
close to the supply pins.
Do not connect.
Negative supply rail (ground) for the digital on-chip circuits.
Negative supply rail (ground) for the digital on-chip circuits.
Output of the on-chip xtal oscillator inverter.
Input to the oscillator inverter from the xtal circuit or external
clock source.
Do not connect.
Do not connect.
C-BUS serial clock input from the µC.
3-state C-BUS serial data output to the µC. This output is
high impedance when not sending data to the µC.
C-BUS serial data input from the µC.
C-BUS chip select input from the µC.
‘wire-Orable’ output for connection to the Interrupt Request
input of the µC. This output is pulled down to DVSS when
active and is high impedance when inactive. An external
pull-up resistor is required.
Digital core supply, nominally 1.8V. Normally this will be
supplied by the on-chip regulator, although an option is
available to use an external regulator. This pin should be
decoupled to DVSS by capacitors mounted close to the
device pins and connected with a power supply track to
DVCORE1. For details see programming register P1.19 in
section in 10.1.2 Program Block 1 – Clock Control.
While booting FI:
SPI: Master Out Slave In (MOSI).
While running FI:
PCM: Serial Data Out.
PCM: Frame Sync Out.
While booting FI:
SPI: Master In Slave Out (MISO).
While running FI:
PCM: Serial Data In.
SPI: Slave Select Out 0.
While booting FI:
SPI: Serial Clock (SCLK).
While running FI:
PCM: Serial Clock Out.
PCM: Frame Sync In.
2012 CML Microsystems Plc
Page 11
D/7261_FI-1.x/9
11 Page | ||
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| PDF Descargar | [ Datasheet CMX7261.PDF ] | |
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