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PDF CMX7861 Data sheet ( Hoja de datos )
| Número de pieza | CMX7861 | |
| Descripción | FirmCODEC | |
| Fabricantes | Consumer Microcircuits Limited | |
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CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CMX7861
FirmCODEC®
D/7861_FI-1.x/2 June 2012
DATASHEET
7861FI-1.x Programmable Baseband Interface
Advance Information
Features
Dual Channel Codecs
o Can operate in modem or codec mode
o Two ADCs 16 bit
o Two DACs 14 bit
o Programmable input and output gain
o Differential/single ended inputs/outputs
Digital Channel Filters
o Two fully-programmable digital filters
o Filter design and configuration support
Auxiliary ADCs
o Four 10-bit DACs
o Autonomous RAMDAC sequencer
Auxiliary ADC
o One 10-bit ADC with four-input MUX
o ADC averaging, trip on high/low ‘watch’ modes
Auxiliary GPIO
o Four programmable input/outputs
Auxiliary Synthesised Clock Generators
o Two programmable clock outputs
C-BUS Host Serial Interface
o SPI-like with register addressing
o Read/write 128-byte FIFOs and data buffers
o Streamline transfers, low host service latency
Master SSP Interface
o External slave device control
o Serial Flash connection
o Pass-through (Thru-port) mode expands host
C-BUS/SPI capacity
Features Cont.
Low-power 3.0V to 3.6V operation
Multiple power-saving options
Small 64-pin VQFN Package
Evaluation support
o PE0601-7861 Evaluation kit
o PE0002 Interface card
Applications
General-purpose DSP analogue/digital
interface
o Sensors
o Control systems
o Telemetry/SCADA/data modems
High Performance Narrowband Data Radio
o DMR
o APCO P25
o Software Defined Radio (SDR)
o 6.25kHz to 25kHz RF channel spacings
o worldwide compatibility e.g. ETSI, FCC,
ARIB, FCC Part 90 per spectral efficiency
requirements
High Performance I/Q Radio Interface
o Tx and Rx: ‘direct connect’ to zero IF
transceiver
o Simple external RC filters
o Digital filter configurable for multiple RF
channel spacings (Rx), Default is for DMR
o I/Q trims
Analogue
System/Signals
Dual Channel Codec
Channel 1 ADC
Channel 2 ADC
Channel 3 DAC
Channel 4 DAC
Auxiliary Operations
ADC
DACs
GPIO
Programmable Digital Filter 1
Programmable Digital Filter 2
Sample Buffers
ADC/DAC Sync
Clock Generation
Power Management
‘Smart’
Function
Engine
FIFO
Configuration
C-BUS
Registers
Function Image™
Clocks Synths
Aux SSP
CMX7861 FirmCODEC®
DSP
Microcontroller
This document contains:
Datasheet
User
Manual
2012 CML Microsystems Plc
1 page  
CMX7861 FirmCODEC® Programmable Baseband Interface
CMX7861
Figure 13 CMX7861 Two-point Tx, Classic FM Limiter-Discriminator Rx .................................... 20
Figure 14 CMX7861 Polar Tx, Amplitude and Phase Rx.............................................................. 20
Figure 15 Basic C-BUS Transactions ........................................................................................... 22
Figure 16 C-BUS Data Streaming Operation................................................................................ 23
Figure 17 FI Loading from Host .................................................................................................... 25
Figure 18 FI Loading from Serial Memory .................................................................................... 26
Figure 19 Tx Mode Processing ..................................................................................................... 32
Figure 20 Rx Mode Processing..................................................................................................... 33
Figure 21 Constellation Diagram – no frequency or phase error.................................................. 34
Figure 22 Constellation Diagram – phase error ............................................................................ 34
Figure 23 Constellation Diagram – frequency error ...................................................................... 34
Figure 24 Received Eye Diagram ................................................................................................. 35
Figure 25 Tx and Rx Data FIFOs.................................................................................................. 36
Figure 26 Main Clock Generation ................................................................................................. 44
Figure 27 Digital System Clock Generation Schemes .................................................................. 45
Figure 28 ADC/DAC Sample Timing Synchronisation .................................................................. 47
Figure 29 C-BUS Timing ............................................................................................................... 56
Figure 30 Mechanical Outline of 64-pin VQFN (Q1) ..................................................................... 57
Information in this datasheet should not be relied upon for final product design. It is always recommended
that you check for the latest product datasheet version from the CML website: [www.cmlmicro.com].
1.3 History
Version Changes
Date
2 Note 32 expanded and Note 48 added in section 8.1.3, to cover dc operation
1 First issue
May 2012
Dec 2011
2012 CML Microsystems Plc
Page 5
D/7861_FI-1.x/2
5 Page 
CMX7861 FirmCODEC® Programmable Baseband Interface
5 External Components
5.1 Xtal Interface
CMX7861
50 XTAL/CLK
49 XTALN
C1
X1
C2
DVSS
X1 For frequency range see
8.1.2 Operating Limits
C1 22pF typical
C2 22pF typical
Figure 3 Recommended External Components - Xtal Interface
Notes:
The clock circuit can operate with either a Xtal or external clock generator. If using an external clock
generator it should be connected to the XTAL/CLK pin and the Xtal and other components are not
required. For external clock generator frequency range see 8.1.2 Operating Limits. When using an
external clock generator the Xtal oscillator circuit may be disabled to save power, see 9.2.3 Program
Block 1 – Clock Control for details. Also refer to section 7.1 Xtal Frequency.
The tracks between the Xtal and the device pins should be as short as possible to achieve maximum
stability and best start up performance. It is also important to achieve a low impedance connection
between the Xtal capacitors and the ground plane.
The DVSS to the Xtal oscillator capacitors C1 and C2 should be of low impedance and preferably be part
of the DVSS ground plane to ensure reliable start up. For correct values of capacitors C1 and C2 refer to
the documentation of the Xtal used.
5.2 C-BUS Interface
DVDD
57 IRQN
56 CSN
55 CDATA
54 RDATA
53 SCLK
R2
R2 10k - 100k
Figure 4 Recommended External Components - C-BUS Interface
Note:
If the IRQN line is connected to other compatible pull-down devices only one pull-up resistor is required
on the IRQN node.
2012 CML Microsystems Plc
Page 11
D/7861_FI-1.x/2
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CMX7861.PDF ] | |
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