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PDF CMX910 Data sheet ( Hoja de datos )
| Número de pieza | CMX910 | |
| Descripción | AIS Baseband Processor | |
| Fabricantes | Consumer Microcircuits Limited | |
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CMX910
AIS Baseband Processor
D/910/6 March 2009
Features:
• Half-Duplex GM(F)SK, FSK and DSC Capabilities
• Slot/Sample Counter with UTC Timing Interface
• Optimum Co-channel and Adjacent-channel
Performance
• Flexible Signal Channels
– Two Simultaneous Rx
– One Tx
– Optional FSK Interface
• AIS Data Formatted and Raw Data Modes
• Supports Carrier-Sensing Channel Access
(CSTDMA) Operation
• RF Device-Enable Facilities
• C-BUS Serial Interface with Expansion Port
Provisional Issue
• I and Q Radio Interface
• Low-Power (3.0 to 3.6V) Operation
• Low Profile, 64-lead LQFP (L9) and
Leadless VQFN (Q1) Packages
• Auxiliary ADC and DAC Functions
– 5 x (10-bit) DACs
– 5-Input MUX (10-bit) ADC
Applications:
• Automatic Identification System
(AIS) for Marine Safety
• Class A or B AIS Transponders
• AIS Rx-only Modules
Radio
Rx1: I/Q
down-
converter
Tx: I/Q
RF up-
converter
Rx2: I/Q
down-
converter
Optional
FSK
Demod.
(FX604)
Aux
ADC
Aux
DACs
CMX910
Σ−Δ
ADCs
Σ−Δ
DACs
Σ−Δ
ADCs
GMSK/
FSK
decoder
GMSK/
FSK
encoder
GMSK/
FSK
decoder
HDLC/
NRZI
decoder
Message
buffer
HDLC/
NRZI
decoder
Message
buffers
HDLC/
NRZI
encoder
Message
buffers
C-BUS
Interface
C-BUS
Expansion
Port
Device
Enable
Port
FSK
Retiming
(External)
Reset and
Power
Control
Slot and
Sample
Timer
Interrupt
Generator
Host µC
Other
C-BUS
Devices
GNSS
Engine
TCXO
1. Brief Description
A highly integrated Baseband Signalling Processor IC, the CMX910 fulfils the requirements of the class A
and class B marine Automatic Identification System (AIS) transponder market. The CMX910 is half duplex
in operation, comprising two parallel I+Q Rx paths and one Tx path. These are configurable for AIS or
DSC operation. The device performs channel filtering and signal modulation/demodulation with
associated AIS functions, such as training sequence detection, NRZI conversion and HDLC processing
(flags, bit stuffing/de-stuffing, CRC generate/check). An external 1200bps FSK demodulator interface
provides a third parallel decode path for DSC, as required by the class A market. Integrated Rx/Tx data
buffers and a flexible slot/sample timer are also provided, all of which greatly reduce the processing
requirements of the host µC. Provision of a C-BUS expansion port, an RF device enable port and a
number of auxiliary ADCs and DACs further simplifies the system hardware design, reducing the overall
equipment cost and size.
© 2009 CML Microsystems Plc
1 page  
AIS Baseband Processor
3. Signal List
Package
Q1 or L9
Signal
Description
CMX910
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
AVSS
IRX1P
IRX1N
QRX1P
QRX1N
VBIAS
ITXP
ITXN
QTXP
QTXN
AVSS
IRX2P
IRX2N
QRX2P
QRX2N
AVDD
IOVDD
ENAB0
ENAB1
ENAB2
ENAB3
ENAB4
ENAB5
DVSS
FSK_MUTE
FSK_DET
FSK_RXD
REFCLK
RESETN
UTC1PPS
SLOTCLKN
32 IRQN
Type
Power
I/P
I/P
I/P
I/P
O/P
O/P
O/P
O/P
O/P
Power
I/P
I/P
I/P
I/P
Power
Power
O/P
O/P
O/P
O/P
O/P
O/P
Power
I/P
I/P
I/P
I/P
I/P
I/P
O/P
O/P
Analogue negative supply rail (ground)
Receive “I” channel 1, positive input
Receive “I” channel 1, negative input
Receive “Q” channel 1, positive input
Receive “Q” channel 1, negative input
A bias line for the internal circuitry, held at ½ AVDD. This pin must
be decoupled to AVSS by a capacitor mounted close to the device
pins
Transmit “I” channel, positive output
Transmit “I” channel, negative output
Transmit “Q” channel, positive output
Transmit “Q” channel, negative output
Analogue negative supply rail (ground)
Receive “I” channel 2, positive input
Receive “I” channel 2, negative input
Receive “Q” channel 2, positive input
Receive “Q” channel 2, negative input
Analogue positive supply rail. Decouple to AVSS
Digital I/O positive supply rail. Decouple to DVSS
Enable output 0
Enable output 1
Enable output 2
Enable output 3
Enable output 4
Enable output 5
Digital negative supply rail (ground)
FSK RF squelch indicator
FSK baseband energy detect indicator
Raw FSK demodulator input data
Master input clock (multiple of 2.4MHz)
Active low chip reset
1Hz UTC sync pulse, typically from GNSS receiver
Slot clock output (active low), pulses at the start of each AIS slot.
Configurable as a ‘wire-ORable’ output, requiring an external pullup
resistor, or as an active pullup/pulldown.
A ‘wire-ORable’ output for connection to the host µC's Interrupt
Request input. This output has a low impedance pull down to DVSS
when active and is high impedance when inactive. An external
pullup resistor is required.
© 2009 CML Microsystems Plc
5
D/910/6
5 Page 
AIS Baseband Processor
CMX910
C-BUS register name
Addr R/W/ Size C-BUS register name
Cmd
Addr R/W/ Size
Cmd
Reset and power control
General_Reset
$01 Cmd
FSK Interface
- FSK_FIFO (DS)
$50 R
8
Clock_Control
$02 W
8 FSK_FIFO_Threshold
$51 W
8
Slot and Sample Timer
Slot_Sample_Control
$10 W
FSK_Status
8 FSK_Control
$52 R
$53 W
16
8
Slot_Sample_Count
Sleep_Sample
$11 R
$12 W
32 Auxiliary ADC
16 ADC0
$60 R
16
Wakeup_Sample
$13 W
16 ADC1
$61 R
16
Slot_Sample_UTC1PPS
$14 R
32 ADC2
$62 R
16
Slot_Nudge
$15 W
16 ADC3
$63 R
16
Sample_Nudge
$16 W
16 ADC4
$64 R
16
Nudge_Trigger
$17 W
16 ADC_Control1
$65 W
8
Max_Auto_Nudge
$18 W
16 ADC_Control2
$66 W
8
Transmit Channel
Tx_FIFO (DS)
$20 W
ADC_Status
8 ADC_Convert
$67 R
$68 Cmd
8
-
Tx_FIFO_Threshold
Tx_Status
$21 W
$22 R
8 Auxiliary DACs
16 DAC0
$70 W
16
Tx_Slot
$23 W
16 DAC1
$71 W
16
Tx_Bits
$24 W
16 DAC2
$72 W
16
Tx_Control
$25 W
16 DAC2
$73 W
16
CSTDMA_Threshold
$26 W
16 DAC4
$74 W
16
Receive Channel 1
Rx1_FIFO (DS)
$30 R
DAC_Control
8 DAC0_Rampup
$75 W
$76 Cmd
8
-
Rx1_FIFO_Threshold
$31 W
8 DAC0_Rampdown
$77 Cmd
-
Rx1_Status
Rx1_Slot
$32 R
$33 R
16 DAC0_Timestep
16 DAC_RAM_Load (DS)
$78 W
$79 W
8
16
Rx1_Sample
Rx1_Bytes
$34 R
$35 R
16 Interrupts
16 Interrupt
$80 R
16
Rx1_Control
$36 W
8 Interrupt_Enable
$81 W
16
Rx1_FreqErr
Rx1_RSSI
$37 R
$38 R
16 Device Enable Port
16 ENAB
$90 W
8
Receive Channel 2
Rx2_FIFO (DS)
$40 R
ENAB_Mask
8 ENAB_Invert
$91 W
$92 W
8
8
Rx2_FIFO_Threshold
Rx2_Status
$41 W
$42 R
8 C-BUS Expansion Port
16 CBUS_Expand
$A0 W
8
Rx2_Slot
Rx2_Sample
$43 R
$44 R
16 Special Command Interface
16 SPC_In0
$B0 W
16
Rx2_Bytes
$45 R
16 SPC_In1
$B1 W
16
Rx2_Control
$46 W
8 SPC_Out0
$B2 R
16
Rx2_FreqErr
$47 R
16 Special_Command
$B4 W
8
Rx2_RSSI
$48 R
16
(DS) - These registers are capable of data-streaming transactions.
Note: C-BUS addresses $F0 to $FE are allocated for production testing and should not be accessed in normal operation.
Table 1 Summary of C-BUS Registers
© 2009 CML Microsystems Plc
11
D/910/6
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CMX910.PDF ] | |
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