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기능 Direct Conversion Receivers
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CMX994A 데이터시트, 핀배열, 회로
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CMX994/CMX994A/CMX994E
Direct Conversion Receivers
CMX994 / CMX994A (lower power consumption) / CMX994E (enhanced performance)
D/994_994A_994E/1 September 2015
DATASHEET
Provisional
Features
Applications
Direct conversion receiver family with PowerTrade™
Analogue/digital multi-mode radio
flexible power vs. performance modes
Software Defined Radio (SDR)
CMX994 - Standard and low power modes
Data telemetry modems
CMX994A - Standard and additional low power modes Satellite communications
CMX994E - Enhanced, standard and low power modes Constant envelope and linear modulation
Rx single conversion to zero IF, near-zero IF or low IF; zero Rx function compatible with CMX998
IF eliminates image responses
Cartesian Feedback Loop Transmitter
Very high mixer IIP2 for practical zero IF receiver
Narrowband e.g. 25kHz, 12.5kHz, 6.25kHz
100MHz to 1000MHz I/Q demodulator (CMX994A/E)
Wideband Data e.g. >1MHz bandwidth
100MHz to 940MHz I/Q demodulator (CMX994)
Extended operation down to 50MHz
LNA with gain control
Precise filtering with 1:2:4 bandwidth select control
Mixer Bandwidth up to 20MHz
Local Oscillator
LO synthesiser
VCO negative resistance amplifier
Rx LO divide by 2, 4 or 6 modes
Tx LO Output with divide by 1, 2, 4, or 6 modes
3.0V 3.6V Low power Operation
Small size 40-pin VQFN Package
I/Q Signals
CMX994
T/R
CMX994A
C-BUS
CMX994E
Reset
Ref. Osc. Direct Conversion Receiver Rx Enable
Tx LO
Tx Enable
Baseband
Signal Processing
µC Flash
1 Brief Description
The CMX994/CMX994A/CMX994E is a family of direct conversion receiver ICs with PowerTrade™, the ability
to dynamically select power vs. performance modes to optimise operating trade-offs. All three devices
include a broadband LNA with gain control followed by a high dynamic range, very high IIP2, I/Q
demodulator. The receiver baseband section includes amplifiers and precise, configurable bandwidth,
baseband filter stages. LO generation is provided by an integer-N PLL and a VCO negative resistance amplifier;
an external LO may also be used. LO dividers are provided for flexible multi-band operation. The devices
operate from a single 3.3V supply over a temperature range of 40°C to +85°C and are available in a small 40-
pin VQFN (Q4) package.
Relative to the CMX994 the CMX994A enables a significant reduction in power by allowing LO phase
correction to be turned off. A further reduction is made possible by the facility to disable either the I or Q
channel. The CMX994E expands on that by adding an enhanced performance mode that features improved
intermodulation in the receive path mixers.
2015 CML Microsystems Plc
Page 1 of 70
D/994_A_E/1




CMX994A pdf, 반도체, 판매, 대치품
Direct Conversion Receivers
Table
Table 1 Definition of Power Supply and Reference Voltages
Table 2 Decoupling Components
Table 3 LNA S11 and S22 Impedances and Parallel Equivalent Circuit in 50Ω
Table 4 LNA S11 and S22 Impedances and Parallel Equivalent Circuit in 100Ω Mode
Table 5 150MHz LNA and Inter-stage Components (100Ω output mode)
Table 6 450MHz LNA and Inter-stage Components (100Ω output mode)
Table 7 900MHz LNA and Inter-stage Components (50Ω output mode)
Table 8 CMX994 Rx Mixer Input Impedances and Parallel Equivalent Circuit
Table 9 CMX994A/CMX994E Rx Mixer Input Impedances and Parallel Equivalent Circuit
Table 10 Receiver Components
Table 11 Internal VCO Amplifier Tank Circuit for 440MHz Operation
Table 12 3rd Order Loop Filter Circuit Values
Table 13 Tx (or Rx) Enable Operation
Table 14 DC OffsetCorrection Adjustments
Table 15 Typical LNA Gain Step Sizes at 100MHz, ZO=100Ω
Table 16 Typical LNA Gain Step Sizes at 450MHz, ZO=100Ω
Table 17 Typical LNA Gain Step Sizes at 940MHz, ZO=50Ω
Table 18 50MHz LNA and Inter-stage Components (100Ω mode)
Table 19 Summary of Results for the Complete Rx Chain at 50MHz
Table 20 Modulation/Modem Combinations
Figure
Figure 1 Block Diagram
Figure 2 Recommended Power Supply Connections and Decoupling
Figure 3 LNA S11 (50Ω Mode)
Figure 4 LNA S22 (50Ω Mode)
Figure 5 LNA S11 (100Ω Mode)
Figure 6 LNA S22 (100Ω Mode)
Figure 7 Recommended LNA Configuration and Inter-stage Match
Figure 8 Rx Mixer Impedance
Figure 9 Recommended Receiver Circuit
Figure 10 Example External Components VCO External Tank Circuit
Figure 11 Example External Components PLL Loop Filter
Figure 12 Simplified Schematic of How DC Offset Corrections are Applied
Figure 13 Baseband I/Q Filtering
Figure 14 Schematic Representation of Filters Used in the I and Q Paths
Figure 15 Local Oscillator
Figure 16 C-BUS Transactions
Figure 17 CMX994 and CMX7164 with FI-2 Typical 4FSK Sensitivity (19.2kbps)
Figure 18 I/Q Path DC Offsets
Figure 19 Example Variation in Voffset with Gain Control Setting
Figure 20 Gain Control
Figure 21 Variation of LNA Gain and IMD with IM Register Setting, 450MHz
Figure 22 I/Q Filter Response
Figure 23 Baseband Intermodulation Test at circa 6Vp-p Differential Output
Figure 24 External Baseband Circuit Connections to Mixer
Figure 25 Rx Mixer Output Bandwidth
2015 CML Microsystems Plc
Page 4 of 70
CMX994/CMX994A/CMX994E
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D/994_A_E/1

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CMX994A 전자부품, 판매, 대치품
Direct Conversion Receivers
4 Pin and Signal List
CMX994/CMX994A/CMX994E
Pin No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
EXPOSED
METAL PAD
Pin Name
IFLT2N
IFLT1P
IFLT1N
VCCRXIF
VCCLNA
LNAIN
LNAOUT
VCCRF
MIXIN
TXLO
VCCLO
LOP
LON
VCOP1
VCOP2
VCON1
VCON2
VCCSYNTH
FREF
DO
DGND
TXEN
RXEN
CSN
RDATA
SCLK
CDATA
RESETN
DVDD
VDDIO
RREF
QFLT1N
QFLT1P
QFLT2N
QFLT2P
RXQP
RXQN
RXIP
RXIN
IFLT2P
AGND
Type
IP
IP
IP
PWR
PWR
IP
OP
PWR
IP
OP
PWR
IP
IP
IP
IP
IP
IP
PWR
IP
OP
PWR
IP
IP
IP
TSOP
IP
IP
IP
PWR
PWR
IP
IP
IP
IP
IP
OP
OP
OP
OP
IP
PWR
Pin Function
I channel 2nd filter capacitor negative
I channel 1st filter capacitor positive
I channel 1st filter capacitor negative
Supply for baseband circuits
Supply for LNA
LNA input
LNA output
Supply for RF circuits
Rx mixer input
LO output for Tx
Supply for LO sections
PLL LO positive input
PLL LO negative input
PLL VCO positive input 1
PLL VCO positive input 2
PLL VCO1 negative input 1
PLL VCO1 negative input 2
Supply to Integer N PLL
Reference frequency input
PLL Charge Pump output
Digital ground
Tx Enable
Rx Enable
C-BUS Chip Select
C-BUS Data output
C-BUS Clock input
C-BUS Data input
C-BUS/Device Reset (Reset when pin Low)
Supply to digital circuits
Supply to C-BUS circuits
Reference resistor for I/Q Filters
Q channel 1st filter capacitor negative
Q channel 1st filter capacitor positive
Q channel 2nd filter capacitor negative
Q channel 2nd filter capacitor positive
RxQ positive output
RxQ negative output
RxI positive output
RxI negative output
I channel 2nd filter capacitor positive
The exposed metal pad must be electrically connected to
analogue ground.
Total = 41 Pins (40 pins and central, exposed metal ground pad)
2015 CML Microsystems Plc
Page 7 of 70
D/994_A_E/1

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