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PDF LPC18S57 Data sheet ( Hoja de datos )
| Número de pieza | LPC18S57 | |
| Descripción | 32-bit ARM Cortex-M3 MCU | |
| Fabricantes | NXP Semiconductors | |
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LPC18S5x/S3x
32-bit ARM Cortex-M3 MCU; up to 1 MB flash and 136 kB
SRAM; Ethernet, two High-speed USB, LCD, EMC, AES engine
Rev. 1 — 24 February 2015
Product data sheet
1. General description
The LPC18S5x/S3x are ARM Cortex-M3 based microcontrollers for embedded
applications. The ARM Cortex-M3 is a next generation core that offers system
enhancements such as low power consumption, enhanced debug features, and a high
level of support block integration.
The LPC18S5x/S3x operate at CPU frequencies of up to 180 MHz. The ARM Cortex-M3
CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local
instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3
CPU also includes an internal prefetch unit that supports speculative branching.
The LPC18S5x/S3x include up to 1 MB of flash and 136 kB of on-chip SRAM, 16 kB of
EEPROM memory, a quad SPI Flash Interface (SPIFI), a State-configurable Timer/PWM
(SCTimer/PWM) subsystem, two High-speed USB controllers, Ethernet, LCD, an external
memory controller, and multiple digital and analog peripherals.
For additional documentation related to the LPC18xx parts, see Section 17 “References”.
2. Features and benefits
Processor core
ARM Cortex-M3 processor (version r2p1), running at CPU frequencies of up to
180 MHz.
ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
Non-maskable Interrupt (NMI) input.
JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.
Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
System tick timer.
On-chip memory
Up to 1 MB on-chip dual bank flash memory with flash accelerator.
16 kB on-chip EEPROM data memory.
136 kB SRAM for code and data use.
Multiple SRAM blocks with separate bus access.
64 kB ROM containing boot code and on-chip software drivers.
64 bit+ 256 bit of One-Time Programmable (OTP) memory for general-purpose
use.
AES engine for encryption and decryption of the boot image and data with DMA
support and programmable via a ROM-based API.
1 page  
NXP Semiconductors
4.1 Ordering options
Table 2. Ordering options
LPC18S5x/S3x
32-bit ARM Cortex-M3 microcontroller
LPC18S57JET256
LPC18S57JBD208
LPC18S37JBD144
LPC18S37JET100
1 MB 512 kB
1 MB 512 kB
1 MB 512 kB
1 MB 512 kB
512 kB
512 kB
512 kB
512 kB
136 kB
136 kB
136 kB
136 kB
yes yes yes yes/yes
yes yes yes yes/yes
no yes yes yes/yes
no yes yes yes/yes
yes yes 8
yes yes 8
yes no 8
no no 4
[1] J = -40 °C to +105 °C; F = -40 °C to +85 °C.
J 164
J 142
J 83
J 49
LPC18S5X_S3X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 February 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
5 of 152
5 Page 
NXP Semiconductors
Table 3. Pin description …continued
Pin name
LPC18S5x/S3x
32-bit ARM Cortex-M3 microcontroller
Description
P1_8
P1_9
P1_10
P1_11
R7 H5 51 71 [2] N; I/O GPIO1[1] — General purpose digital input/output pin.
PU O U1_DTR — Data Terminal Ready output for UART1.
O CTOUT_12 — SCTimer/PWM output 12. Match output 3 of
timer 3.
I/O EMC_D1 — External memory data line 1.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O SD_VOLT0 — SD/MMC bus voltage select output 0.
T7 J5 52 73 [2] N; I/O GPIO1[2] — General purpose digital input/output pin.
PU O U1_RTS — Request to Send output for UART1.
O CTOUT_11 — SCTimer/PWM output 11. Match output 3 of
timer 2.
I/O EMC_D2 — External memory data line 2.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
I/O SD_DAT0 — SD/MMC data bus line 0.
R8 H6 53 75 [2] N; I/O GPIO1[3] — General purpose digital input/output pin.
PU I U1_RI — Ring Indicator input for UART1.
O CTOUT_14 — SCTimer/PWM output 14. Match output 2 of
timer 3.
I/O EMC_D3 — External memory data line 3.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
I/O SD_DAT1 — SD/MMC data bus line 1.
T9 J7 55 77 [2] N; I/O GPIO1[4] — General purpose digital input/output pin.
PU I U1_CTS — Clear to Send input for UART1.
O CTOUT_15 — SCTimer/PWM output 15. Match output 3 of
timer 3.
I/O EMC_D4 — External memory data line 4.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
I/O SD_DAT2 — SD/MMC data bus line 2.
LPC18S5X_S3X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 February 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
11 of 152
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