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LPC18S37 데이터시트 PDF




NXP Semiconductors에서 제조한 전자 부품 LPC18S37은 전자 산업 및 응용 분야에서
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부품번호 LPC18S37 기능
기능 32-bit ARM Cortex-M3 MCU
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LPC18S37 데이터시트, 핀배열, 회로
LPC18S5x/S3x
32-bit ARM Cortex-M3 MCU; up to 1 MB flash and 136 kB
SRAM; Ethernet, two High-speed USB, LCD, EMC, AES engine
Rev. 1 — 24 February 2015
Product data sheet
1. General description
The LPC18S5x/S3x are ARM Cortex-M3 based microcontrollers for embedded
applications. The ARM Cortex-M3 is a next generation core that offers system
enhancements such as low power consumption, enhanced debug features, and a high
level of support block integration.
The LPC18S5x/S3x operate at CPU frequencies of up to 180 MHz. The ARM Cortex-M3
CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local
instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3
CPU also includes an internal prefetch unit that supports speculative branching.
The LPC18S5x/S3x include up to 1 MB of flash and 136 kB of on-chip SRAM, 16 kB of
EEPROM memory, a quad SPI Flash Interface (SPIFI), a State-configurable Timer/PWM
(SCTimer/PWM) subsystem, two High-speed USB controllers, Ethernet, LCD, an external
memory controller, and multiple digital and analog peripherals.
For additional documentation related to the LPC18xx parts, see Section 17 “References”.
2. Features and benefits
Processor core
ARM Cortex-M3 processor (version r2p1), running at CPU frequencies of up to
180 MHz.
ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
Non-maskable Interrupt (NMI) input.
JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.
Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
System tick timer.
On-chip memory
Up to 1 MB on-chip dual bank flash memory with flash accelerator.
16 kB on-chip EEPROM data memory.
136 kB SRAM for code and data use.
Multiple SRAM blocks with separate bus access.
64 kB ROM containing boot code and on-chip software drivers.
64 bit+ 256 bit of One-Time Programmable (OTP) memory for general-purpose
use.
AES engine for encryption and decryption of the boot image and data with DMA
support and programmable via a ROM-based API.




LPC18S37 pdf, 반도체, 판매, 대치품
NXP Semiconductors
LPC18S5x/S3x
32-bit ARM Cortex-M3 microcontroller
4. Ordering information
Table 1. Ordering information
Type number
Package
Name
Description
Version
LPC18S57JET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC18S57JBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm
SOT459-1
LPC18S37JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm
SOT486-1
LPC18S37JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC18S5X_S3X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 February 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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LPC18S37 전자부품, 판매, 대치품
NXP Semiconductors
6. Pinning information
6.1 Pinning
ball A1
LPC18S57JET256
index area 2 4 6 8 10 12 14 16
1 3 5 7 9 11 13 15
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
aaa-016765
Transparent top view
Fig 2. Pin configuration LBGA256 package
LPC18S5x/S3x
32-bit ARM Cortex-M3 microcontroller
ball A1
index area
LPC18S37JET100
1 2 3 4 5 6 7 8 9 10
A
B
C
D
E
F
G
H
J
K
aaa-016766
Transparent top view
Fig 3. Pin configuration TFBGA100 package
157 104
109 72
LPC18S57JBD208
LPC18S37JBD144
208 53
144 37
aaa-016767
Fig 4. Pin configuration LQFP208 package
aaa-016768
Fig 5. Pin configuration LQFP144 package
6.2 Pin description
On the LPC18S5x/S3x, digital pins are grouped into 16 ports, named P0 to P9 and PA to
PF, with up to 20 pins used per port. Each digital pin can support up to eight different
digital functions, including General-Purpose I/O (GPIO), selectable through the SCU
registers.
The pin name is not indicative of the GPIO port assigned to it.
The parts contain two 10-bit ADCs (ADC0 and ADC1). The input channels of ADC0 and
ADC1 on dedicated pins and multiplexed pins are combined in such a way that all channel
0 inputs (named ADC0_0 and ADC1_0) are tied together and connected to both, channel
LPC18S5X_S3X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 February 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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부품번호상세설명 및 기능제조사
LPC18S37

32-bit ARM Cortex-M3 MCU

NXP Semiconductors
NXP Semiconductors

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