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NPIC6C596 데이터시트 PDF




NXP Semiconductors에서 제조한 전자 부품 NPIC6C596은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 NPIC6C596 기능
기능 Power logic 8-bit shift register
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NPIC6C596 데이터시트, 핀배열, 회로
NPIC6C596
Power logic 8-bit shift register; open-drain outputs
Rev. 2 — 4 July 2013
Product data sheet
1. General description
The NPIC6C596 is an 8-bit serial-in/serial or parallel-out shift register with a storage
register and open-drain outputs. Both the shift and storage register have separate clocks.
The device features a serial input (DS) and a serial output (Q7S) to enable cascading and
an asynchronous reset MR input. A LOW on MR resets both the shift register and storage
register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in
the shift register is transferred to the storage register on a LOW-to-HIGH transition of the
STCP input. If both clocks are connected together, the shift register is always one clock
pulse ahead of the storage register. To provide additional hold time in cascaded
applications, the serial output QS7 is clocked out on the falling edge of SHCP. Data in the
storage register drives the gate of the output extended-drain NMOS (EDNMOS) transistor
whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to
assume a high-impedance OFF-state. Operation of the OE input does not affect the state
of the registers.
The open-drain outputs are 33 V/100 mA continuous current extended-drain NMOS
transistors designed for use in systems that require moderate load power such as LEDs.
Integrated voltage clamps in the outputs provide protection against inductive transients
making the device suitable for power driver applications such as relays, solenoids and
other low-current or medium-voltage loads.
2. Features and benefits
Specified from 40 C to +125 C
Low RDSon
Eight Power EDNMOS transistor outputs of 100 mA continuous current
250 mA current limit capability
Output clamping voltage 33 V
30 mJ avalanche energy capability
Enhanced cascading for multiple stages
All registers cleared with single input
Low power consumption
ESD protection:
HBM JDS-001 Class 2 exceeds 2500 V
CDM JESD22-C101E exceeds 1000 V




NPIC6C596 pdf, 반도체, 판매, 대치품
NXP Semiconductors
NPIC6C596
Power logic 8-bit shift register; open-drain outputs
SHCP
OE
DS
STCP
MR
Q1
76543210
Fig 6. Timing diagram
5V
GND
5V
GND
5V
GND
5V
GND
5V
GND
VOH
VOL
aaa-002553
NPIC6C596
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 July 2013
© NXP B.V. 2013. All rights reserved.
4 of 21

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NPIC6C596 전자부품, 판매, 대치품
NXP Semiconductors
NPIC6C596
Power logic 8-bit shift register; open-drain outputs
7.1 Test circuit and waveform
WORD
GENERATOR(1)
5V
15 V
7
MR
VCC
1
lD
15
SHCP
2
DS
DUT
3-6,
11-14
Qn
10
STCP
8
OE GND
16
30 Ω
1.5 mH
VDS
ID
VDS
tw(2)
tAL
5V
0V
lAL = 200 mA
V(BR)DSS = 33 V
min
aaa-002556
(1) The word generator has the following characteristics: tr, tf 10 ns; ZO = 50 .
(2) The input pulse duration (tW) is increased until peak current IAL = 200 mA. Energy test level is defined as:
EAS = IAL V(BR)DSS tAL/2 = 30 mJ.
Fig 9. Test circuit and waveform for measuring single-pulse avalanche energy
8. Recommended operating conditions
Table 4.
Symbol
VCC
VI
ID
Tamb
Recommended operating conditions
Parameter
Conditions
supply voltage
input voltage
drain current
pulsed drain output current;
VCC = 5 V; Tamb = 25 C;
all outputs on
ambient temperature
[1] Pulse duration 100 s and duty cycle 2 %.
[2] Technique should limit Tj Tamb to 10 C maximum.
9. Static characteristics
Min
4.5
0
[1][2] -
Typ Max
- 5.5
- 5.5
- 250
40 - +125
Unit
V
V
mA
C
Table 5. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VCC = 5.0 V; Tamb = 25 C
Min Typ Max
VIH HIGH-level input VCC = 4.5 V to 5.5 V
voltage
0.85VCC
-
-
VIL LOW-level input VCC = 4.5 V to 5.5 V
voltage
- - 0.15VCC
VOH HIGH-level
serial data output Q7S; VI = VIH or VIL
output voltage
IO = 20 A; VCC = 4.5 V
IO = 4 mA; VCC = 4.5 V
4.4 4.49
4.0 4.2
-
-
Unit
V
V
V
V
NPIC6C596
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 July 2013
© NXP B.V. 2013. All rights reserved.
7 of 21

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