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CH7025 데이터시트 PDF




Chrontel에서 제조한 전자 부품 CH7025은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 CH7025 기능
기능 TV/VGA Encoder
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CH7025 데이터시트, 핀배열, 회로
Chrontel
CH7025/CH7026
Brief Datasheet
CH7025/CH7026 TV/VGA Encoder
Features
General Description
TV encoder targets the handheld devices and other appropriate The CH7025/CH7026 is a device targeting
display devices used in consumer products. (i.e. automobile) handheld and similar systems which accept digital
Support multiple output formats. Such as SDTV format (NTSC input signal, and encodes and transmits data
and PAL), HDTV format for 480p,576p,720p and 1080i,
analog RGB output for VGA. Sync signals can be provided in
separated or composite manner (programmable composite sync
through 10-bit DACs. The device is able to encode
the video signals and generate synchronization
generation).
signals SDTV format for NTSC and PAL
Three on-chip 10-bit high speed DACs providing flexible standards and HDTV format for 480p,576p,720p
output capabilities. Such as single, double or triple CVBS and 1080i. Analog RGB output and composite
outputs, YPbPr output, RGB output and simultaneous CVBS SYNC signal are also supported. The device
and S-video outputs.
accepts different data formats including RGB and
16Mbits SDRAM is used as frame buffer. Supporting for frame
rate conversion.
Flexible up and down scaling engine is embedded including de-
flickering capability.
Programmable 24-bit/18-bit/16-bit/15-bit/12-bit/8-bit digital
YCbCr (e.g. RGB565, RGB666, RGB888, ITU656
like YCbCr, etc.). 16Mbit SDRAM is embedded in
package. Frame rate conversion and Image rotation
are possible.
input interface supports various RGB (RGB888, RGB666,
RGB565 and etc), YCbCr (4:4:4 YCbCr, ITU656) and 2x or 3x
multiplexed input. CPU interface are also supported.
Support for flexible input resolution up to 800x800 and
1024x680.
Pixel by pixel brightness, contrast, hue and saturation
adjustment for each kind of output is supported. (For RGB
output, only brightness and contrast adjustment is supported).
Pixel by pixel horizontal position adjustment and line by line
vertical position adjustment are supported.
90/180/270 degree image rotation and vertical or horizontal flip
functions are supported.
Macrovision 7.1.L1 for SDTV is supported in CH7025.
(CH7026 is Non-Macrovision part.)
MacrovisionTM copy protection support for progressive scan
TV (480p, 576p CH7025 only)
CGMS-A support for SDTV and HDTV
TV/Monitor connection detect capability. DAC can be switched
off based on detection result. (Driver support is required)
Programmable power management.
Flexible pixel clock frequency from graphics controller is
supported. (2.3MHz –120MHz) Flexible input clock from
crystal or oscillator is supported. (2.3MHz – 64MHz)
Only slave mode supported.
Offered in BGA or QFP package.
Fully programmable through serial port.
IO and SPC/SPD voltage supported is from 1.2V to 3.3V.
Note: the above feature list is subject to change without notice. Please contact Chrontel for more information
and current updates.
209-1000-004 Rev. 1.1, 12/3/2008
1




CH7025 pdf, 반도체, 판매, 대치품
CHRONTEL
CH7025/CH7026
HSO
VSO
CSYNC
ATPG
AS
ResetB
AGND
AVDD
GNDQ_MEM
VDDQ_MEM
AGND
AVDD
GND_MEM
VDD_MEM
NC
NC
NC
VDDQ_MEM
GNDQ_MEM
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60 D[8]
59 D[7]
58 D[6]
57 D[5]
56 D[4]
55 D[3]
54 D[2]
53 D[1]
CH7025/CH7026
52
51
D[0]
VDDIO
50 GCLK
49 AVDD
48 AGND
47 GND_MEM
46 GND_MEM
45 VDD_MEM
44 VDD_MEM
43 NC
42 NC
41 NC
Figure 3: 80 Pin LQFP Package
4 209-1000-004 Rev. 1.1, 12/3/2008

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CH7025 전자부품, 판매, 대치품
CHRONTEL
CH7025/CH7026
Table 2: Pin Name Descriptions (LQFP80 Package)
Pin #
52 - 67
70 - 77
79
Type
In
In/Out
Symbol
D[23:0]
V
Description
Data[0] through Data[23] Inputs
These pins accept the 24 data inputs from a digital video port of a
graphics controller. The swing is defined by VDDIO.
Vertical Sync Input / Output
When the SYO control bit is low, this pin accepts a vertical sync input
for use with the input data. The amplitude will be 0 to VDDIO.
78
In/Out
H/WEB
When the SYO control bit is high, the device will output a vertical
sync pulse. The output is driven from the VDDIO supply.
Horizontal Sync Input / Output
When the SYO control bit is low, this pin accepts a horizontal sync
input for use with the input data. The amplitude will be 0 to VDDIO.
When the SYO control bit is high, the device will output a horizontal
sync pulse. The output is driven from the VDDIO supply.
80 In
DE/CSB
5 In AS
4 In ATPG
6 In ResetB
38
In/Out
SPD
39 In
SPC
29 Out DAC0
27 Out DAC1
25 Out DAC2
31 In
ISET
It is also the WEB signal of CPU interface.
Data Input Indicator
When the pin is high, the input data is active.
When the pin is low, the input data is blanking.
CSB signal input of CPU interface
The amplitude will be 0 to VDDIO.
Chip address select
0: 76h
1: 75h
ATPG Enable
(Internally pull-down)
This pin should be left open or pulled low with a 10k resistor in the
application. This pin configures the pre-condition for scan chain and
boundary scan test when high. Otherwise it should be low. Voltage
level is 0 to 3.3V.
Reset * Input
When this pin is low, the device is held in the power-on reset
condition. When this pin is high, reset is controlled through the serial
port.
Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial port.
External pull-up resister is required.
Serial Port Clock Input
This pin functions as the clock pin of the serial port. External pull-up
resister is required.
CVBS, S-video, YPbPr or Analog RGB output
Full swing is up to 1.3v
CVBS, S-video, YPbPr or Analog RGB output
Full swing is up to 1.3v
CVBS, S-video, YPbPr or Analog RGB output
Full swing is up to 1.3v
Current Set Resistor Input
This pin sets the DAC current. A 1.2k , 1% tolerance resistor should
209-1000-004 Rev. 1.1, 12/3/2008
7

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