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PDF RTM560-266R Data sheet ( Hoja de datos )
| Número de pieza | RTM560-266R | |
| Descripción | Clock Generator | |
| Fabricantes | RealTek | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de RTM560-266R (archivo pdf) en la parte inferior de esta página. Total 29 Páginas | ||
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Clock Generator
General Description
The RTM 560-266R is a single chip frequency generator for VIA KT266 system. The clock chip
provides standard serial bus for programming device function. Based on the function above, the
spread spectrum can be enable for reducing EMI. And RTM 560-266R also builds in the testability
function.
Features
! Support Up to 200 MHz frequency.
! Power Down feature.
! Spread Spectrum for EMI control.
! Output features:
" 1 pairs – CPU differential open drain.
" 1 pairs - CPU [email protected].
" 11- PCI @3.3V.
" 1- 48MHz, @3.3V fixed.
" 1- 24_48# MHz, @3.3V fixed.
" 3- REF @3.3V, 14.318MHz.
" 3- AGP @3.3V
VDD_3.3
GND
X1
X2
VDD_3.3
FS2*/48MHz
FS3*/24_48MHz
GND
FS4*/PCIF
PCI0/*SEL24/48#
PCI1
GND
PCI2
PCI3
VDD_3.3
PCI4
PCI5
PCI6
GND
PCI7
PCI8
PCI9_E
VDD_3.3
SRESET#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 FS0*/REF0
47 FS1*/REF1
46 REF2
45 REF_STOP#
44 AGP_STOP#
43 GND
42 CPUCLKT0
41 CPUCLKC0
40 VDD_2.5
39 CPUCLKT_CS
38 CPUCLKC_CS
37 GND
36 CPU_STOP#
35 PCI_STOP#
34 PD#
33 VDD_3.3
32 GND
31 SDATA
30 SCLK
29 GND
28 AGP2
27 AGP1
26 AGP0
25 VDD_3.3
X1
X2
sclk
sdata
CONTROL
PIN
XTAL OSC
Serial bus
interface
PLL1
PLL2
DIVIDER
MULTIPLEX
REF
OUTPUT
DELAY
STOP
TRISTATE
CLOCK
OUTPUT
CONTROL
LOGIC
01/04/13
-1-
1 page  
Clock Generator
Standard Serial Bus Control:
Support standard serial bus block-mode and word-mode.
The Block Mode:
1 7 11 8 1 8 1
S Slave Address W A Command Code A Byte Count=N A
0D2h
Dummy
Dummy
8181
Data 1 A Data 2 A
8
Data N
11
AP
Block Write
1 7 11 8 11 7 11
S Slave Address W A Command Code A S Slave Address R A
0D2h
Dummy
0D3h
818181
Byte Count=N A Data 1 A Data 2 A
Active register count
8
Data N
Block Read
11
AP
The Word Mode:
1 7 11 8 1 8 1 8 11
S Slave Address W A Command Code A Low Byte A High Byte A P
0D2h
Index
Dummy
Data1
Write Word
1 7 11 8 11 7 11
S Slave Address W A Command Code A S Slave Address R A
0D2h
Index
0D3h
8 1 8 11
High Byte A Low Byte A P
*Index Data
*Index Data
Note slave address is D2h.
Read Word
01/04/13
-5-
5 Page 
Clock Generator
Power Down Function
PD# CPUCLK
0 Low
1 On
AGP PCICLK REF 24MHz 48MHz Osc VCOs
Low Low Low Low Low Off Off
On On On On On On On
Power Down Waveform
10 ns
PD#
CPU 100MHz
AGP 66MHz
PCI 33MHz
REF 14.318MHz
48MHz 48MHz
24MHz 24MHz
posedge 1 posedge 2
waiting negedge
negedge 1
negedge 1 negedge 1
negedge 1
negedge 1
negedge 1
negedge 1
Note
1. After PD# is sampled active (Low) for 2 consecutive rising edges of CPUCLK, all the output clocks are driven Low on their next High to Low transition.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
01/04/13
- 11 -
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet RTM560-266R.PDF ] | |
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