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P3P623S00E 데이터시트 PDF




ON Semiconductor에서 제조한 전자 부품 P3P623S00E은 전자 산업 및 응용 분야에서
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부품번호 P3P623S00E 기능
기능 Peak EMI Reduction IC
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P3P623S00E 데이터시트, 핀배열, 회로
P3P623S00B,
P3P623S00E
Product Preview
Timing-Safet Peak EMI
Reduction IC
Functional Description
P3P623S00B/E is a versatile, 3.3 V Zero−delay buffer designed to
distribute Timing−Safe clocks with Peak EMI reduction. P3P623S00B
is an eight−pin version, accepts one reference input and drives out one
low−skew Timing−Safe clock. P3P623S00E accepts one reference
input and drives out eight low−skew Timing−Safe clocks.
P3P623S00B/E has an SS% that selects 2 different Deviation and
associated Input−Output Skew (TSKEW). Refer to the Spread
Spectrum Control and Input−Output Skew table for details.
P3P623S00E has a CLKOUT for adjusting the Input−Output clock
delay, depending upon the value of capacitor connected at this pin to
GND.
P3P623S00B/E operates from a 3.3 V supply and is available in two
different packages, as shown in the ordering information table.
Application
P3P623S00B/E is targeted for use in Displays and memory interface
systems.
General Features
Clock Distribution with Timing−Safe Peak EMI Reduction
Input Frequency Range: 20 MHz − 50 MHz
2 Different Spread Selection Options
Spread Spectrum can be Turned ON/OFF
External Input−Output Delay Control Option
Supply Voltage: 3.3 V ± 0.3 V
P3P623S00B: 8 Pin SOIC
P3P623S00E: 16 Pin TSSOP
The First True Drop−in Solution
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
www.onsemi.com
8
1
SOIC−8 NB
CASE 751
TSSOP−16
CASE 948AN
PIN CONFIGURATION
CLKIN 1
8 NC
NC 2
SS% 3
P3P623S00B
7 VDD
6 CLKOUT
GND 4
5 SSON
CLKIN 1
CLKOUT1 2
VDD 3
SS% 4
GND 5
CLKOUT2 6
CLKOUT3 7
DLY_CTRL 8
P3P623S00E
16 CLKOUT
15 CLKOUT7
14 CLKOUT6
13 VDD
12 GND
11 CLKOUT5
10 CLKOUT4
9 SSON
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2015
February, 2015 − Rev. P3
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Publication Order Number:
P3P623S00/D




P3P623S00E pdf, 반도체, 판매, 대치품
P3P623S00B, P3P623S00E
Table 5. OPERATING CONDITIONS
Parameter
Description
VDD
Operating Voltage
TA Operating Temperature (Ambient Temperature)
CL Load Capacitance
CIN Input Capacitance
Table 6. ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min
VIL Input Low Voltage (Note 5)
VIH Input High Voltage (Note 5)
IIL Input LOW Current
VIN = 0 V
IIH Input HIGH Current
VIN = VDD
VOL
Output LOW Voltage (Note 6)
IOL = 8 mA
VOH Output HIGH Voltage (Note 6) IOH = −8 mA
IDD Supply Current
Unloaded outputs
ZO Output Impedance
2.0
2.4
5. CLKIN input has a threshold voltage of VDD/2
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Table 7. SWITCHING CHARACTERISTICS
Parameter
Test Conditions
Input Frequency
Output Frequency
30 pF load
Duty Cycle (Notes 7, 8) = (t2/ t1) x 100
Output Rise Time (Notes 7, 8)
Measured at VDD/2
Measured between 0.8 V and 2.0 V
Output Fall Time (Notes 7, 8)
Measured between 2.0 V and 0.8 V
Output−to−Output Skew (Notes 7, 8) All outputs equally loaded with SSOFF
Delay, CLKIN Rising Edge to
CLKOUT Rising Edge (Note 8)
Measured at VDD/2 with SSOFF
Min
20
20
40
Device−to−Device Skew (Note 8)
Measured at VDD/2 on the CLKOUT
pins of the device
Cycle−to−Cycle Jitter (Notes 7, 8)
PLL Lock Time (Note 8)
Loaded outputs
Stable power supply, valid clock presen-
ted on CLKIN pin
7. All parameters specified with 30 pF loaded outputs.
8. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Min
3.0
−40
Typ
23
Typ
50
Max Unit
3.6 V
+85 °C
30 pF
7 pF
Max Units
0.8 V
V
50 mA
100 mA
0.4 V
V
27 mA
W
Max
50
50
60
2.5
2.5
250
±350
700
±250
1.0
Units
MHz
MHz
%
nS
nS
pS
pS
pS
pS
mS
www.onsemi.com
4

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P3P623S00E 전자부품, 판매, 대치품
P3P623S00B, P3P623S00E
PACKAGE DIMENSIONS
−X−
A
SOIC−8 NB
CASE 751−07
ISSUE AK
B
−Y−
−Z−
H
85
S 0.25 (0.010) M Y M
1
4
K
G
D
C
SEATING
PLANE
N X 45 _
0.10 (0.004)
M
J
0.25 (0.010) M Z Y S X S
SOLDERING FOOTPRINT*
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0_ 8_ 0_ 8_
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
ǒ ǓSCALE 6:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
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