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PDF ISL80505 Data sheet ( Hoja de datos )
| Número de pieza | ISL80505 | |
| Descripción | High Performance 500mA LDO | |
| Fabricantes | Intersil | |
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DATASHEET
High Performance 500mA LDO
ISL80505
The ISL80505 is a single output Low Dropout voltage regulator
(LDO) capable of sourcing up to 500mA output current. This
LDO operates from input voltages of 1.8V to 6V. The output
voltage of ISL80505 can be programmed from 0.8V to 5.5V.
A submicron BiCMOS process is utilized for this product family
to deliver the best in class analog performance and overall
value. This CMOS LDO consumes significantly lower quiescent
current as a function of load compared to bipolar LDOs, which
translates into higher efficiency and packages with smaller
footprints.
State-of-the-art internal compensation achieves a very fast
load transient response and excellent PSRR. The ISL80505
provides an output accuracy of ±1.8% VOUT accuracy over all
load, line and temperature variation (TJ = -40°C to +125°C).
An external capacitor on the soft-start pin provides an
adjustable soft starting of the output voltage ramp to control
the inrush current. The ENABLE feature allows the part to be
placed into a low quiescent current shutdown mode.
Table 1 shows the differences between the ISL80505 and
others in its family.
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER INPUT VOLTAGE RANGE MAX OUTPUT CURRENT
ISL80510
2.2V to 6V
1.0A
ISL80505
1.8V to 6V
0.5A
Features
• ±1.8% VOUT accuracy guaranteed over line, load and
TJ = -40°C to +125°C
• Very low 45mV dropout voltage at VOUT = 2.5V
• Stable with a 4.7µF output ceramic capacitor
• Very fast transient response
• Programmable output soft-start time
• Excellent PSRR over wide frequency range
• Current limit protection
• Thermal shutdown function
• Available in an 8 Ld DFN package
• Pb-free (RoHS compliant)
Applications
• Noise sensitive instrumentation systems
• Post regulation of switched mode power supplies
• Industrial systems
• Medical equipment
• Telecommunications and networking equipment
• Servers
• Hard disk drives (HD/HDD)
Related Literature
UG044, “ISL80510EVAL1Z Evaluation Board User Guide”
VIN
CIN
CSS
VIN 8
VIN 7
SS 6
ENABLE
5
ISL80505
EPAD
1 VOUT
2 VOUT
FB
3
4 GND
VOUT
R1 COUT
CPB
(OPTIONAL)
R2
FIGURE 1. TYPICAL APPLICATION CIRCUIT
80
70
60
50
40
30
20
10
0
100
IOUT = 0.1A
IOUT = 0.3A
IOUT = 0.5A
1k 10k
FREQUENCY (Hz)
FIGURE 2. PSRR
VIN = 2.3V
VOUT = 1.8V
COUT = 10µF
CPB= 2.7nF
R1 = 10kΩ
R2 = 3.83kΩ
100k
1M
September 8, 2015
FN8770.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL80505
Electrical Specifications Unless otherwise noted, 1.8V < VIN < 6V, VOUT = 0.5V, TJ = +25°C. Applications must follow thermal
guidelines of the package to determine worst case junction temperature. Please refer to “Applications Information” on page 10 and Tech Brief TB379.
Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN MAX
(Note 9) TYP (Note 9) UNIT
Output Noise Voltage
VIN = 2.2V; VOUT = 1.8V; ILOAD = 500mA,
BW = 100Hz < f < 100kHz
79 µVRMS
ENABLE PIN CHARACTERISTICS
Turn-on Threshold
0.5 0.8 1 V
Hysteresis
10 80 200 mV
ENABLE Pin Turn-on Delay
ENABLE Pin Leakage Current
SOFT-START CHARACTERISTICS
COUT = 4.7µF, ILOAD = 500mA
VIN = 6V, ENABLE = 3V
100 µs
1 µA
SS Pin Currents (Note 11)
IPD VIN = 3.5V, ENABLE = 0V, SS = 1V
0.5 1 1.3 mA
ICHG
-3.3 -2 -0.8 µA
NOTES:
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
10. Dropout is defined as the difference in supply VIN and VOUT when the output is below its nominal regulation.
11. IPD is the internal pull-down current that discharges the external SS capacitor on disable. ICHG is the current from the SS pin that charges the external
SS capacitor during start-up.
Submit Document Feedback
5
FN8770.0
September 8, 2015
5 Page 
ISL80505
Additional capacitors of any value in ceramic, POSCAP,
alum/tantalum electrolytic types may be placed in parallel to
improve PSRR at higher frequencies and/or load transient AC
output voltage tolerances.
INPUT CAPACITOR
For proper operation, a minimum capacitance of 4.7µF X5R/X7R
is required at the input. This ceramic input capacitor must be
connected to the VIN and GND pins of the LDO with PCB traces no
longer than 0.5cm.
PHASE BOOST CAPACITOR (CPB)
A small phase boost capacitor, CPB, can be placed across the top
resistor, R1, in the feedback resistor divider network in order to
improve the AC performances of the LDO for the applications
where the output capacitor is 10µF or larger. For 10µF output
capacitor, the recommended CPB value can be calculated by
using Equation 4.
CPB = 2--------x----6---0--1-0----0---x----R----1--
(EQ. 4)
This zero increases the crossover frequency of the LDO and
provides additional phase resulting in faster load transient
response.
Power Dissipation and Thermals
The junction temperature must not exceed the range specified in
the “Recommended Operating Conditions” on page 4. The power
dissipation can be calculated by using Equation 5:
PD = VIN – VOUT IOUT + VIN IGND
(EQ. 5)
The maximum allowable junction temperature, TJ(MAX) and the
maximum expected ambient temperature, TA(MAX), determine
the maximum allowable power dissipation, as shown in
Equation 6:
PDMAX = TJMAX – TA JA
(EQ. 6)
JA is the junction-to-ambient thermal resistance.
For safe operation, ensure that the power dissipation PD,
calculated from Equation 5, is less than the maximum allowable
power dissipation PD(MAX).
The DFN package uses the copper area on the PCB as a heatsink.
The EPAD of this package must be soldered to the copper plane
(GND plane) for effective heat dissipation. Figure 29 shows a
curve for the JA of the DFN package for different copper area
sizes.
49
47
45
43
41
39
372 4 6 8 10 12 14 16 18 20 22 24
EPAD-MOUNT COPPER LAND AREA ON PCB, mm2
FIGURE 29. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB WITH
THERMAL VIAS JA vs EPAD-MOUNT COPPER LAND
AREA ON PCB
Thermal Fault Protection
The power level and the thermal impedance of the package
(+48°C/W for DFN) determine when the junction temperature
exceeds the thermal shutdown temperature. In the event that the
die temperature exceeds around +160°C, the output of the LDO will
shut down until the die temperature cools down to about +130°C.
Current Limit Protection
The ISL80505 LDO incorporates protection against overcurrent due
to any short or overload condition applied to the output pin. The LDO
performs as a constant current source when the output current
exceeds the current limit threshold noted in the “Electrical
Specifications” table on page 4. If the short or overload condition is
removed from VOUT, then the output returns to normal voltage
regulation mode. In the event of an overload condition, the LDO may
begin to cycle on and off due to the die temperature exceeding
thermal fault condition and subsequently cooling down after the
power device is turned off.
PC Board Layout
The performances of this LDO depend greatly on the care taken
in designing the PC board. The following are recommendations to
achieve optimum performance.
• A minimum capacitance of 4.7µF X5R/X7R ceramic input
capacitor must be placed to the VIN and GND pins of the LDO
with PCB traces no longer than 0.5cm.
• A minimum capacitance of 4.7µF X5R/X7R ceramic output
capacitor must be placed to the VOUT and GND pins of the LDO
with PCB traces no longer than 0.5cm.
• Connect the EPAD to the ground plane with low-thermal
resistance vias.
Submit Document Feedback 11
FN8770.0
September 8, 2015
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| PDF Descargar | [ Datasheet ISL80505.PDF ] | |
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