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8V31012 데이터시트 PDF




IDT에서 제조한 전자 부품 8V31012은 전자 산업 및 응용 분야에서
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부품번호 8V31012 기능
기능 Differential HCSL Fanout Buffer
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8V31012 데이터시트, 핀배열, 회로
1-to-12, Differential HCSL Fanout Buffer
8V31012
DATA SHEET
General Description
The 8V31012 is a 1-to-12 Differential HCSL Fanout Buffer. The
8V31012 is designed to translate any differential signal levels to
differential HCSL output levels. An external reference resistor is
used to set the value of the current supplied to an external
load/termination resistor. The load resistor value is chosen to equal
the value of the characteristic line impedance of 50. The 8V31012
is characterized at an operating supply voltage of 3.3V.
The differential HCSL outputs, accurate crossover voltage and duty
cycle make the 8V31012 ideal for interfacing to PCI Express and
FBDIMM applications.
Features
Twelve differential HCSL outputs
Translates any differential input signal (LVPECL, LVHSTL, LVDS,
HCSL) to HCSL levels without external bias networks
Maximum output frequency: 250MHz
Output skew: 265ps (typical)
VOH: 850mV (maximum)
Full 3.3V supply voltage
Available in lead-free (RoHS 6) package
-40°C to 85°C ambient operating temperature
Block Diagram
CLK
nCLK
Q6
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
Q10
nQ10
Q11
nQ11
IREF
8V31012 REVISION 1 10/21/15
Pin Assignment
Q0
nQ0
Q0
nQ0
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
VDD
nQ9
Q1
nQ1
VDD 3
Q1 4
34 Q9
33 GND
nQ1 5
32 nQ8
Q2 GND 6
31 Q8
nQ2
Q2 7
8V31012
30 VDD
Q3 nQ2 8
29 nQ7
nQ3
VDD 9
28 Q7
Q4
nQ4
Q5
Q3
nQ3
VDD
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
VDD
nQ6
Q6
nQ5
48-pin, 7mm x 7mm VFQFN Package
1 ©2015 Integrated Device Technology, Inc.




8V31012 pdf, 반도체, 판매, 대치품
8V31012 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, VDD
Inputs, VI
Outputs, IO
Maximum Junction Temperature
Storage Temperature, TSTG
Rating
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
125°C
-65C to 150C
DC Electrical Characteristics
Table 2A. Power Supply DC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VDD Core Supply Voltage
IDD Power Supply Current
Output Unterminated
3.135
Typical
3.3
Maximum
3.465
105
Units
V
mA
Table 2B. Differential DC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Input
IIH
CLK, nCLK
High Current
VDD = VIN = 3.465V
Input
IIL
CLK, nCLK
Low Current
VDD = 3.465V, VIN = 0V
VPP
VCMR
Peak-to-Peak Voltage1
Common Mode Input Voltage1, 2
NOTE 1. VIL should not be less than -0.3V.
NOTE 2. Common mode input voltage is defined as VIH.
0.15
GND + 0.5
Typical
Maximum
5
5
1.3
VDD – 0.85
Units
µA
µA
V
V
1-TO-12, DIFFERENTIAL HCSL FANOUT BUFFER
4
REVISION 1 10/21/15

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8V31012 전자부품, 판매, 대치품
8V31012 DATA SHEET
Applications Information
Recommendations for Unused Output Pins
Outputs:
Differential Outputs
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 2 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1= VDD/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V1in the center of the input voltage swing. For
example, if the input clock is driven from a single-ended 2.5V
LVCMOS driver and the DC offset (or swing center) of this signal is
1.25V, the R1 and R2 values should be adjusted to set the V1 at
1.25V. The values below are for when both the single ended swing
and VDD are at the same voltage. This configuration requires that the
sum of the output impedance of the driver (Ro) and the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the input will attenuate the signal in half. This
can be done in one of two ways. First, R3 and R4 in parallel should
equal the transmission line impedance. For most 50applications,
R3 and R4 can be 100. The values of the resistors can be increased
to reduce the loading for slower and weaker LVCMOS driver. When
using single-ended signaling, the noise rejection benefits of
differential signaling are reduced. Even though the differential input
can handle full rail LVCMOS signaling, it is recommended that the
amplitude be reduced while maintaining an edge rate faster than
1V/ns. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
REVISION 1 10/21/15
7 1-TO-12, DIFFERENTIAL HCSL FANOUT BUFFER

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8V31012

Differential HCSL Fanout Buffer

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