PDF F1953 Data sheet ( Hoja de datos )

Número de pieza	F1953
Descripción	6-bit Digital Step Attenuator
Fabricantes	Integrated Device Technology
Logotipo
Hay una vista previa y un enlace de descarga de F1953 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas
No Preview Available ! 6-bit Digital Step Attenuator GENERAL DESCRIPTION This document describes the specification for the IDTF1953 Digital Step Attenuator. The F1953 is part of a family of Glitch-FreeTM DSAs optimized for the demanding requirements of communications Infrastructure. These devices are offered in a compact 4x4 QFN package with 50 Ω impedances for ease of integration. COMPETITIVE ADVANTAGE Digital step attenuators are used in Receivers and Transmitters to provide gain control. The IDTF1953 is a 6-bit step attenuator optimized for these demanding applications. The silicon design has very low insertion loss and low distortion (> +60 dBm IP3I.) The device has pinpoint accuracy and settles to final attenuation value within 400 nsec. Most importantly, the F1953 includes IDT’s Glitch-FreeTM technology which results in less than 0.5 dB of overshoot ringing during MSB transitions. This is in stark contrast to competing DSAs that glitch as much as 10 dB (see p. 10.)  Lowest insertion loss for best SNR  Glitch-FreeTM when transitioning – won’t damage PA or ADC  Extremely accurate with low distortion Glitch-FreeTTMM APPLICATIONS  Base Station 2G, 3G, 4G, TDD radiocards  Repeaters and E911 systems  Digital Pre-Distortion  Point to Point Infrastructure  Public Safety Infrastructure  WIMAX Receivers and Transmitters  Military Systems, JTRS radios  RFID handheld and portable readers  Cable Infrastructure PART# MATRIX Part# F1950 F1951 F1952 F1953 Freq range 150 - 4000 100 - 4000 Resolution / Range 0.25 / 31.75 0.50 / 31.5 Control Parallel & Serial Serial Only IL -1.3 -1.2 Pinout PE43702 PE43701 HMC305 100 – 4000 400 - 4000 0.50 / 15.5 0.50 / 31.5 Serial Only Parallel & Serial -0.9 HMC305 PE4302 -1.3 DAT-31R5 F1953 DATASHEET 400 to 4000 MHz IDTF1953 FEATURES  Glitch-FreeTM, < 0.6 dB transient overshoot  Spurious Free Design  2.7 to 3.3 V supply  Attenuation Error < 0.5 dB @ 2 GHz  Low Insertion Loss < 1.4 dB @ 2 GHz  Excellent Linearity >+60 dBm IP3I  Fast settling time, < 400 nsec  Serial or Parallel Interface 31.5 dB Range  Stable Integral Non-Linearity over temperature  Low Power Consumption < 200 uA  Integrated DC blocking capacitors  Drop-In replacement  4x4 mm Thin QFN 20 pin package DEVICE BLOCK DIAGRAM RF1 RF2 Bias DEC SPI VMODE VDD 6 D[5:0] CLK DATA LE ORDERING INFORMATION Omit IDT prefix 0.8 mm height package IDTF1953NCGI8 Tape & Reel RF product Line Green Industrial Temp range Glitch-FreeTM Digital Step Attenuator 1 Rev2 April2014 1 page F1953 DATASHEET 6-bit Digital Step Attenuator 400 to 4000 MHz IDTF1953 PARALLEL CONTROL MODE The user has the option of running in one of two parallel modes: Direct Parallel Mode or Latched Parallel Mode. DIRECT-PARALLEL MODE: Direct-parallel mode is selected when VMODE (pin 13) is < VIL and LE (pin 5) is > VIH. In this mode the device will immediately react to any voltage changes to the parallel control pins [pins 1, 15, 16, 17, 19, 20]. Use direct-parallel mode for the fastest settling time. LATCHED-PARALLEL MODE: Latched-parallel mode is selected when VMODE (pin 13) is < VIL and LE (pin 5) is toggled from < VIL to > VIH To utilize latched-parallel mode:  Set LE < VIL  Adjust pins [1, 15, 16, 17, 19, 20] to the desired attenuation setting. (Note the device will not react to these pins while LE < VIL.)  Pull LE > VIH. The device will then transition to the attenuation settings reflected by these pins. When the device is powered up In Latched Parallel Mode [VMODE < VIL and LE < VIL], the attenuation setting defaults to the state defined by the six parallel data pins [pins 1, 15, 16, 17, 19, 20] LATCHED PARALLEL MODE TIMING DIAGRAM: (Note the Timing Spec Intervals in Blue) VMODE Spec Interval s LE A C DB Data Word Latched into Active Register D[5:0] LATCHED PARALLEL MODE TIMING TABLE: Interval Symbol A B C D Description Serial to Parallel Mode Setup Time Parallel Data Hold Time LE minimum pulse width Parallel Data Setup Time Glitch-FreeTM Digital Step Attenuator Min Spec 100 10 10 10 Max Spec Units nsec nsec nsec nsec 5 Rev2 April2014 5 Page 6-bit Digital Step Attenuator PIN DIAGRAM TOP View (looking through the top of the package) F1953 DATASHEET 400 to 4000 MHz IDTF1953 D5 1 RF1 2 DATA 3 CLK 4 LE 5 20 19 18 17 16 Exposed Pad Package Drawing 4 mm x 4 mm package dimension 2.06 mm x 2.06 mm exposed pad 0.5 mm pitch 20 pins 0.75 mm height 0.25 mm pad width 0.55 mm pad length 15 D4 14 RF2 13 VMODE 12 GND [internal NC] 11 GND [internal NC] 6 7 8 9 10 * Device is RF Bi-Directional Glitch-FreeTM Digital Step Attenuator 11 Rev2 April2014 11 Page

Páginas	Total 17 Páginas
PDF Descargar	[ Datasheet F1953.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
F1953	6-bit Digital Step Attenuator	Integrated Device Technology

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar