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PDF NVT224 Data sheet ( Hoja de datos )
| Número de pieza | NVT224 | |
| Descripción | Remote Thermal Monitor and Fan Controller | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NVT224
dbCOOLt Remote Thermal
Monitor and Fan Controller
The NVT224 dbCOOL controller is a thermal monitor and multiple
PWM fan controller for noise−sensitive or power−sensitive
applications requiring active system cooling. The NVT224 can drive a
fan using either a low or high frequency drive signal, monitor the
temperature of up to two remote sensor diodes plus its own internal
temperature, and measure and control the speed of up to four fans so
that they operate at the lowest possible speed for minimum acoustic
noise.
The automatic fan speed control loop optimizes fan speed for a
given temperature. The effectiveness of the system’s thermal solution
can be monitored using the THERM input. The NVT224 also provides
critical thermal protection to the system using the bidirectional
THERM pin as an output to prevent system or component overheating.
The NVT224 has been through Automotive Qualification according
to AEC−Q100 Grade 1 standards.
Features
• Controls and Monitors Up to 4 Fans
• High and Low Frequency Fan Drive Signal
• 1 On−Chip and 2 Remote Temperature Sensors
• Extended Temperature Measurement Range, Up to 191°C
• Automatic Fan Speed Control Mode Controls System Cooling Based
on Measured Temperature
• Enhanced Acoustic Mode Dramatically Reduces User Perception of
Changing Fan Speeds
• Thermal Protection Feature via THERM Output
• Monitors Performance Impact of Intel PentiumR 4 Processor
• Thermal Control Circuit via THERM Input
• 3−Wire and 4−Wire Fan Speed Measurement
• Limit Comparison of All Monitored Values
• Meets SMBus 2.0 Electrical Specifications
(Fully SMBus 1.1 Compliant)
• Automotive Qualification According to AEC−Q100 Grade 1
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
http://onsemi.com
MARKING
DIAGRAM
QSOP−16
CASE 492
NVT
224
YYWWG
A
NVT224 = Specific Device Code
YYWW = Date Code
G = Pb−Free Package
A = Bottom Marking
PIN ASSIGNMENT
SCL 1
GND 2
VCC 3
TACH3
PWM2/
SMBALERT
TACH1
4
5
6
TACH2 7
PWM3 8
NVT224
TOP VIEW
16 SDA
15 PWM1/XTO
14 VCCP
13 D1+
12 D1–
11 D2+
10 D2–
9
TACH4/GPIO/THERM
SMBALERT
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 57 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
August, 2012 − Rev. 1
1
Publication Order Number:
NVT224/D
1 page  
NVT224
ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1)
Parameter
Conditions
Min Typ Max Unit
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, VIH
Input Low Voltage, VIL
DIGITAL INPUT CURRENT
0.75 x VCC
V
0.8 V
Input High Current, IIH
Input Low Current, IIL
Input Capacitance, CIN
SERIAL BUS TIMING
VIN = VCC
VIN = 0 V
See Note 2 and Figure 2
±1 mA
±1 mA
5 pF
Clock Frequency, fSCLK
10 400 kHz
Glitch Immunity, tSW
50 ns
Bus Free Time, tBUF
4.7 ms
SCL Low Time, tLOW
4.7 ms
SCL High Time, tHIGH
4.0 50 ms
SCL, SDA Rise Time, tR
1000
ns
SCL, SDA Fall Time, tF
300 ns
Data Setup Time, tSU: DAT
250 ns
Detect Clock Low Timeout, tTIMEOUT
Can be optionally disabled
15
35 ms
1. All voltages are measured with respect to GND, unless otherwise specified. Typicals are at TA = 25°C and represent the most likely
parametric norm. Logic inputs accept input high voltages of up to VMAX, even when the device is operating down to VMIN. Timing
specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge.
2. SMBus timing specifications are guaranteed by design and are not production tested.
SCL
tLOW tR
tHD: STA
tHD: DAT
tF
tHIGH
tSU: DAT
tHD: STA
tSU: STA
SDA
tBUF
PS
S
Figure 2. Serial Bus Timing Diagram
tSU: STO
P
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5
5 Page 
NVT224
connected to a common SMBALERT line connected to the
master. If a device’s SMBALERT line goes low, the
following events occur:
1. SMBALERT is pulled low.
2. The master initiates a read operation and sends the
alert response address (ARA = 0001 100). This
general call address must not be used as a specific
device address.
3. The device whose SMBALERT output is low
responds to the alert response address, and the
master reads its device address. The address of the
device is now known and can be interrogated in
the usual way.
4. If more than one device’s SMBALERT output is
low, the one with the lowest device address has
priority in accordance with normal SMBus
arbitration.
5. Once the NVT224 has responded to the alert
response address, the master must read the status
registers, and the SMBALERT is cleared only if
the error condition has gone away.
SMBus Timeout
The NVT224 includes an SMBus timeout feature. If there
is no SMBus activity for 35 ms, the NVT224 assumes that
the bus is locked and releases the bus. This prevents the
device from locking or holding the SMBus expecting data.
Some SMBus controllers cannot handle the SMBus timeout
feature, so it can be disabled.
Configuration Register 1 (0x40)
Bit 6 TODIS = 0; SMBus timeout enabled (default).
Bit 6 TODIS = 1; SMBus timeout disabled.
Virus Protection
To prevent rogue programs or viruses from accessing
critical NVT224 register settings, the lock bit can be set.
Setting Bit 1 of Configuration Register 1 (0x40) sets the lock
bit and locks critical registers. In this mode, certain registers
can no longer be written to until the NVT224 is powered
down and powered up again. For more information on which
registers are locked, see the Register Tables section.
Voltage Measurement Input
The NVT224 has one external voltage measurement
channel. It can also measure its own supply voltage, VCC.
Pin 14 can measure VCCP. The VCC supply voltage
measurement is carried out through the VCC pin (Pin 3). The
VCCP input can be used to monitor a chipset supply voltage
in computer systems.
Analog−to−Digital Converter
All analog inputs are multiplexed into the on−chip,
successive approximation, analog−to−digital converter.
This has a resolution of 10 bits. The basic input range is 0 V
to 2.25 V, but the input has built−in attenuators to allow
measurement of VCCP without any external components. To
allow for the tolerance of the supply voltage, the ADC
produces an output of 3/4 full scale (decimal 768 or 300 hex)
for the nominal input voltage and so has adequate headroom
to deal with overvoltages.
Input Circuitry
The internal structure for the VCCP analog input is shown
in Figure 19. The input circuit consists of an input protection
diode, an attenuator, and a capacitor to form a first−order,
low−pass filter that gives the input immunity to high
frequency noise.
VCCP
17.5kW
52.5kW
35pF
Figure 19. Structure of Analog Inputs
Voltage Measurement Registers
Register 0x21, VCCP Reading = 0x00 default
Register 0x22, VCC Reading = 0x00 default
VCCP Limit Registers
Associated with the VCCP measurement channel is a high
and low limit register. Exceeding the programmed high or
low limit causes the appropriate status bit to be set.
Exceeding either limit can also generate SMBALERT
interrupts.
Register 0x46, VCCP Low Limit = 0x00 default
Register 0x47, VCCP High Limit = 0xFF default
Table 2 shows the input ranges of the analog inputs and
output codes of the 10−bit ADC.
When the ADC is running, it samples and converts a
voltage input in 711 ms and averages 16 conversions to
reduce noise; a measurement takes nominally 11.38 ms.
Extended Resolution Registers
Voltage measurements can be made with higher accuracy
using the extended resolution registers (0x76 and 0x77).
Whenever the extended resolution registers are read, the
corresponding data in the voltage measurement registers is
locked until their data is read. That is, if extended resolution
is required, then the extended resolution register must be
read first, immediately followed by the appropriate voltage
measurement register.
Additional ADC Functions for Voltage Measurements
A number of other functions are available on the NVT224
to offer the system designer increased flexibility.
Turn−Off Averaging
For each voltage measurement read from a value register,
16 readings have been made internally, and the
results averaged, before being placed into the value register.
For instances where faster conversions are needed, setting
Bit 4 of Configuration Register 2 (0x73) turns averaging off.
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| PDF Descargar | [ Datasheet NVT224.PDF ] | |
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