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PDF P3PSL450A Data sheet ( Hoja de datos )
| Número de pieza | P3PSL450A | |
| Descripción | Peak EMI reduction IC | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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P3PSL450A
Low Voltage, Timing-Safe]
Peak EMI Reduction IC
Functional Description
P3PSL450A/AH is a versatile low voltage peak EMI reduction IC
based on Timing−Safe technology. P3PSL450A/AH accepts one input
from an external reference, and locks on to it delivering a 1x
Timing−Safe output clock. P3PSL450A/AH has a Frequency
Selection (FS) control that facilitates selecting one of the two
frequency ranges within the operating frequency range. Refer
frequency Selection table. The device has an SSEXTR pin to select
different deviations depending upon the value of an external resistor
connected at this pin to GND. P3PSL450A/AH has an MR pin for
selecting one of the two Modulation Rates. PD# provides the Power
Down option.
P3PSL450A is a Low drive part and P3PSL450AH is a High drive
part. Refer to DC/AC Electrical characteristic table.
P3PSL450A/AH operates over a supply voltage range of 1.8 V $
0.2 V, and is available in an 8 Pin WDFN (2 mm x 2 mm) Package.
General Features
• 1x, LVCMOS Timing−Safe Peak EMI Reduction
• Input Clock Frequency: 15 MHz − 60 MHz
• Output Clock Frequency (Timing−Safe): 15 MHz − 60 MHz
• Analog Frequency Deviation Selection
• Two different Modulation Rate Selection Option
• Power Down option for Power Save
• Low and High Drive Parts
• Supply Voltage: 1.8 V $ 0.2 V
• 8 Pin WDFN (2 mm X 2 mm) Package
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Application
• P3PSL450A/AH is targeted for use in consumer electronic
applications like mobile phones, Camera modules, MFP and DPF
MR VDD SSEXTR
http://onsemi.com
1
WDFN8
CASE 511AQ
MARKING
DIAGRAM
1 XX MG
G
XX = Specific Device Code
M = Date Code
G = Pb−Free Device
PIN CONFIGURATION
CLKIN 1
FS 2
PD# 3
GND 4
8 VDD
7 SSEXTR
6 MR
5 ModOUT
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
CLKIN
PLL
© Semiconductor Components Industries, LLC, 2010
July, 2010 − Rev. 1
PD# GND
FS
Figure 1. Block Diagram
1
ModOUT
(Timing−Safe)
Publication Order Number:
P3PSL450A/D
1 page  
P3PSL450A
DEVIATION VERSUS SSEXTR RESISTANCE CHARTS
3.0
FS = 0,
2.5 MR = 0
2.0
1.5
1.0
0.5
0.00 100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
Figure 6. Deviation vs SSEXTR Chart
(CLKIN = 15 MHz)
3.0
FS = 0,
2.5 MR = 1
2.0
1.5
1.0
0.5
0.00 100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
Figure 7. Deviation vs SSEXTR Chart
(CLKIN = 15 MHz)
3
FS = 0,
2.5 MR = 0
2
1.5
1
0.5
0
0 100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
Figure 8. Deviation vs SSEXTR Chart
(CLKIN = 24 MHz)
3
FS = 0,
2.5 MR = 1
2
1.5
1
0.5
0
0 100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
Figure 9. Deviation vs SSEXTR Chart
(CLKIN = 24 MHz)
2.5
FS = 0,
MR = 0
2.0
1.5
1.0
0.5
0.00 100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
Figure 10. Deviation vs SSEXTR Chart
(CLKIN = 30 MHz)
1.5
FS = 0,
MR = 1
1.0
0.5
0.00 100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
Figure 11. Deviation vs SSEXTR Chart
(CLKIN = 30 MHz)
http://onsemi.com
5
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet P3PSL450A.PDF ] | |
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