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74ALVC16245 데이터시트 PDF




ON Semiconductor에서 제조한 전자 부품 74ALVC16245은 전자 산업 및 응용 분야에서
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부품번호 74ALVC16245 기능
기능 Low-Voltage 1.8/2.5/3.3V 16-Bit Transceiver
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74ALVC16245 데이터시트, 핀배열, 회로
74ALVC16245
Low−Voltage 1.8/2.5/3.3V
16−Bit Transceiver
With 3.6 VTolerant Inputs and Outputs
(3State, NonInverting)
The 74ALVC16245 is an advanced performance, noninverting
16bit transceiver. It is designed for very highspeed, very lowpower
http://onsemi.com
operation in 1.8 V, 2.5 V or 3.3 V systems.
The ALVC16245 is designed with byte control. It can be operated as
MARKING DIAGRAM
two separate octals, or with the controls tied together, as a 16bit wide
function. The Transmit/Receive (T/Rn) inputs determine the direction
48
of data flow through the bidirectional transceiver. Transmit
(activeHIGH) enables data from A ports to B ports; Receive
(activeLOW) enables data from B to A ports. The Output Enable
48
1
74ALVC16245DT
AWLYYWW
inputs (OEn), when HIGH, disable both A and B ports by placing them
in a HIGH Z condition.
Designed for Low Voltage Operation: VCC = 1.653.6 V
3.6 V Tolerant Inputs and Outputs
TSSOP48
DT SUFFIX
CASE 1201
1
High Speed Operation: 3.0 ns max for 3.0 to 3.6 V
3.7 ns max for 2.3 to 2.7 V
6.0 ns max for 1.65 to 1.95 V
Static Drive: $24 mA Drive at 3.0 V
A = Assembly
Location
WL = Wafer Lot
YY = Year
WW = Work Week
$12 mA Drive at 2.3 V
$4 mA Drive at 1.65 V
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0 V
Near Zero Static Supply Current in All Three Logic States (40 mA)
ORDERING INFORMATION
Device
Package
Shipping
74ALVC16245DTR TSSOP 2500/Tape & Reel
Substantially Reduces System Power Requirements
Latchup Performance Exceeds $250 mA @ 125°C
ESD Performance: Human Body Model >2000 V; Machine Model >200 V
Second Source to Industry Standard 74ALVC16245
†To ensure the outputs activate in the 3state condition, the output enable pins
should be connected to VCC through a pullup resistor. The value of the resistor is
determined by the current sinking capability of the output connected to the OE pin.
© Semiconductor Components Industries, LLC, 2006
June, 2006 Rev. 1
1
Publication Order Number:
74ALVC16245/D




74ALVC16245 pdf, 반도체, 판매, 대치품
74ALVC16245
DC ELECTRICAL CHARACTERISTICS
Symbol
Characteristic
Condition
VIH HIGH Level Input Voltage (Note 8)
1.65 V VCC < 2.3 V
2.3 V VCC 2.7 V
VIL LOW Level Input Voltage (Note 8)
2.7 V < VCC 3.6 V
1.65 V VCC < 2.3 V
2.3 V VCC 2.7 V
2.7 V < VCC 3.6 V
VOH HIGH Level Output Voltage
VOL LOW Level Output Voltage
II Input Leakage Current
IOZ 3State Output Current
1.65 V VCC 3.6 V; IOH = 100 mA
VCC = 1.65 V; IOH = 4 mA
VCC = 2.3 V; IOH = 6 mA
VCC = 2.3 V; IOH = 12 mA
VCC = 2.7 V; IOH = 12 mA
VCC = 3.0 V; IOH = 12 mA
VCC = 3.0 V; IOH = 24 mA
1.65 V VCC 3.6 V; IOL = 100 mA
VCC = 1.65 V; IOL = 4 mA
VCC = 2.3 V; IOL = 6 mA
VCC = 2.3 V; IOL = 12 mA
VCC = 2.7 V; IOL = 12 mA
VCC = 3.0 V; IOL = 24 mA
1.65 V VCC 3.6 V; 0 V VI 3.6 V
1.65 V VCC 3.6 V; 0 V VO 3.6 V;
VI = VIH or VIL
IOFF PowerOff Leakage Current
ICC Quiescent Supply Current (Note 9)
VCC = 0 V; VI or VO = 3.6 V
1.65 V VCC 3.6 V; VI = GND or VCC
1.65 V VCC 3.6 V; 3.6 V VI, VO 3.6 V
DICC
Increase in ICC per Input
2.7 V < VCC 3.6 V; VIH = VCC 0.6 V
8. These values of VI are used to test DC electrical characteristics only.
9. Outputs disabled or 3state only.
AC CHARACTERISTICS (Note 10; tR = tF = 2.0 ns; CL = 30 pF; RL = 500 W)
Limits
TA = 40°C to +85°C
Min Max
0.65 x VCC
1.7
2.0
0.35 x VCC
0.7
0.8
VCC 0.2
1.2
2.0
1.7
2.2
2.4
2.0
0.2
0.45
0.4
0.7
0.4
0.55
±5.0
±10
10
40
±40
750
Unit
V
V
V
V
mA
mA
mA
mA
mA
mA
TA = 40°C to +85°C
VCC = 3.0 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 1.65 to1.95 V
Symbol
Parameter
Waveform Min Max Min Max Min Max Unit
tPLH Propagation Delay
tPHL Input to Output
1 1.0 3.0 1.0 3.7 1.0 6.0 ns
1.0 3.0 1.0 3.7 1.0 6.0
tPZH
tPZL
Output Enable Time to
High and Low Level
2 1.0 4.4 1.0 5.7 1.0 9.3 ns
1.0 4.4 1.0 5.7 1.0 9.3
tPHZ
tPLZ
Output Disable Time From
High and Low Level
2 1.0 4.1 1.0 5.2 1.0 7.6 ns
1.0 4.1 1.0 5.2 1.0 7.6
tOSHL
tOSLH
OutputtoOutput Skew
(Note 11)
0.5 0.5 0.75 ns
0.5 0.5 0.75
10. For CL = 50 pF, add approximately 300 ps to the AC maximum specification.
11. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGHtoLOW (tOSHL) or LOWtoHIGH (tOSLH); parameter
guaranteed by design.
http://onsemi.com
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74ALVC16245 전자부품, 판매, 대치품
K
t
TOP
COVER
TAPE
B1 K0
SEE
NOTE 2
FOR MACHINE REFERENCE
ONLY
INCLUDING DRAFT AND RADII
CONCENTRIC AROUND B0
74ALVC16245
10 PITCHES
CUMULATIVE
TOLERANCE ON
P0
TAPE
±0.2 mm
D P2 (±0.008")
E
A0 SEE NOTE 2
+ B0
+
P
EMBOSSMENT
USER DIRECTION OF FEED
FW
+
CENTER LINES
OF CAVITY
D1
FOR COMPONENTS
2.0 mm × 1.2 mm
AND LARGER
BENDING RADIUS
R MIN.
TAPE AND COMPONENTS
SHALL PASS AROUND RADIUS R"
WITHOUT DAMAGE
EMBOSSED
CARRIER
*TOP COVER
TAPE THICKNESS (t1)
0.10 mm
(0.004") MAX.
EMBOSSMENT
10° MAXIMUM COMPONENT ROTATION
TYPICAL
COMPONENT CAVITY
CENTER LINE
100 mm
(3.937")
1 mm MAX
TAPE
TYPICAL
COMPONENT
CENTER LINE
1 mm
250 mm
(0.039") MAX (9.843")
CAMBER (TOP VIEW)
ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm
Figure 6. Carrier Tape Specifications
EMBOSSED CARRIER DIMENSIONS (See Notes 1 and 2)
Tape
Size
B1
Max
D
D1 E
F
K
P P0 P2 R T W
24mm
20.1mm
(0.791")
1.5 + 0.1mm
−0.0
(0.059
+0.004" −0.0)
1.5mm
Min
(0.060")
1.75
±0.1 mm
(0.069
±0.004")
11.5
±0.10 mm
(0.453
±0.004")
11.9 mm
Max
(0.468")
16.0
±0.1 mm
(0.63
±0.004")
4.0
±0.1 mm
(0.157
±0.004")
2.0
±0.1 mm
(0.079
±0.004")
30 mm
(1.18")
0.6 mm 24.3 mm
(0.024") (0.957")
1. Metric Dimensions GovernEnglish are in parentheses for reference only.
2. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0.50 mm max. The component cannot rotate more than 10° within the determined cavity.
http://onsemi.com
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