|
|
PDF STDVE001A Data sheet ( Hoja de datos )
| Número de pieza | STDVE001A | |
| Descripción | Adaptive single 3.4 Gbps TMDS/HDMI signal equalizer | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de STDVE001A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
STDVE001A
Adaptive single 3.4 Gbps TMDS/HDMI signal equalizer
Preliminary Data
Features
■ Compatible with the high-definition multimedia
interface (HDMI) v1.3 digital interface
■ Conforms to the transition minimized
differential signaling (TMDS) voltage standard
on input and output channels
■ 340 MHz maximum clock speed operation
supports all video formats with deep color at
maximum refresh rates
■ 3.4 Gbps data rate per channel
■ Fully automatic adaptive equalizer for cables
lengths up to 25 m
■ Single supply VCC: 3.135 to 3.465 V
■ ESD: ±8 KV contact for all I/Os
■ Integrated open-drain I2C buffer for display
data channel (DDC)
■ 5.3 V tolerant DDC and HPD I/Os
■ Lock-up free operation of I2C bus
■ 0 to 400 kHz clock frequency for I2C bus
■ Low capacitance of all the channels
■ Equalizer regenerates the incoming attenu-
ated TMDS signal
■ Buffer drives the TMDS outputs over long PCB
track lengths
■ Low output skew and jitter
■ Tight input thresholds reduce bit error rates
■ On-chip selectable 50 Ω input termination
■ Low ground bounce
■ Data and control inputs provide undershoot
clamp diode
■ Evaluation kit is available
Table 1. Device summary
Order code
Operating temperature
STDVE001ABTR
STDVE001AQTR
-40°C to 85°C
-40°C to 85°C
TQFP48
QFN48
Description
The STDVE001A integrates a 4-channel 3.4 Gbps
TMDS equalizer. High-speed data paths and flow-
through pinout minimize the internal device jitter
and simplify the board layout.
The equalizer overcomes the intersymbol
interference (ISI) jitter effects from lossy cables.
The buffer/driver on the output can drive the
TMDS output signals over long distances. In
addition to this, STDVE001A integrates the 50 Ω
termination resistor on all the input channels to
improve performance and reduce board space.
The device can be placed in a low-power mode by
disabling the output current drivers. The
STDVE001A is ideal for advanced TV and STB
applications supporting HDMI/DVI standard. The
differential signal from the HDMI/DVI ports can be
routed through the STDVE001A to guarantee
good signal quality at the HDMI receiver.
Designed for very low skew, jitter and low I/O
capacitance, the switch preserves the signal
integrity to pass the stringent HDMI compliance
requirements.
Package
TQFP48
QFN48
Packaging
Tape and reel
Tape and reel
July 2008
Rev 2
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/49
www.st.com
49
1 page  
STDVE001A
1 Block diagram
Figure 1. STDVE001A block diagram
Block diagram
4-$3
DIFFERENTIAL
INPUTS
3$!?%84
3#,?%84
$$#?%.
(0$?%84
#%#?)/
)NPUT
TERMINATION
SELECTABLE
)NPUT STAGE
RECEIVER
%QUALIZER
/UTPUT
$RIVER
4RANSMITTER
)#
REPEATER
(0$
DRIVER
4-$3
DIFFERENTIAL
OUTPUTS
3$!?).4
3#,?).4
(0$?).4
#%#?)/?).4
!-6
5/49
5 Page 
STDVE001A
Pin configuration
Table 2. Pin description (continued)
Pin number Pin name
Type
Function
22
OUT_D1+
Output
HDMI 1.3 compliant TMDS output. OUT_D1+ makes a
differential output signal with OUT_D1-.
23
OUT_D1-
Output
HDMI 1.3 compliant TMDS output. OUT_D1- makes a
differential output signal with OUT_D1+.
24
GND
Power Ground
Active low enable signal
OE_N
N_D
termination
IOUT_D outputs
25
OE_N
Input
1
High-Z
High-Z
0 50 Ω
Active
26
VDD_INT
Power
DC supply for DDC, HPD and CEC (can be 5V or 3.3V or
unconnected)
27
GND
Power Ground
28
SCL_INT
I/O
DDC Clock I/O. Pulled-up by external termination to
VCC.
29
SDA_INT
I/O DDC Data I/O. Pulled-up by external termination to VCC.
Sink side, Low-frequency, 0V to 5V (nominal) hot plug
detector input signal.
Voltage high indicates “plugged” state; voltage low
indicates “unplugged” state.
30
HPD_INT
Input
High : 5V power signal asserted from source to sink and
EDID is ready
Low : No 5V power signal is asserted from source to sink
or EDID is not ready
31
GND
Power Ground
I2C repeater enable signal
32
DDC_EN
Input
DDC_EN
I2C repeater
0 V Disabled, high-Z
3.3 V
Enabled, active
33
VCC
Power 3.3 V±10% DC supply
11/49
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet STDVE001A.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| STDVE001A | Adaptive single 3.4 Gbps TMDS/HDMI signal equalizer | STMicroelectronics |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |