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PDF MTY14N100E Data sheet ( Hoja de datos )
| Número de pieza | MTY14N100E | |
| Descripción | Power Field Effect Transistor | |
| Fabricantes | ON Semiconductor | |
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MTY14N100E
TMOS E−FET.™
Power Field Effect
Transistor
N−Channel Enhancement−Mode Silicon
Gate
This advanced TMOS power FET is designed to withstand high
energy in the avalanche and commutation modes. This new energy
efficient design also offers a drain−to−source diode with fast recovery
time. Designed for high voltage, high speed switching applications in
power supplies, converters, PWM motor controls, and other inductive
loads. The avalanche energy capability is specified to eliminate the
guesswork in designs where inductive loads are switched and offer
additional safety margin against unexpected voltage transients.
• Avalanche Energy Specified
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
http://onsemi.com
TMOS POWER FET
14 AMPERES, 1000 VOLTS
RDS(on) = 0.80 W
TO−264
CASE 340G−02
STYLE 1
D
G
®
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−to−Source Voltage
Drain−to−Gate Voltage (RGS = 1.0 MΩ)
Gate−to−Source Voltage — Continuous
— Single Pulse (tp ≤ 50 μs)
VDSS
VDGR
VGS
VGSM
1000
1000
± 20
± 40
Vdc
Vdc
Vdc
Vpk
Drain Current — Continuous
— Continuous @ TC = 100°C
— Single Pulse (tp ≤ 10 μs)
Total Power Dissipation
Derate above 25°C
ID 14 Adc
ID 8.7
IDM 49 Apk
PD 300 Watts
2.4 W/°C
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche Energy — Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 14 Apk, L = 10 mH, RG = 25 Ω )
TJ, Tstg
EAS
−55 to 150
980
°C
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
RθJC
RθJA
0.42 °C/W
30
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Preferred devices are Motorola recommended choices for future use and best overall value.
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 1
1
Publication Order Number:
MTY14N100E/D
1 page  
MTY14N100E
12 420
QT
10
350
VGS
8 280
6
Q1
4
Q2
TJ = 25°C
ID = 14 A
210
140
2 70
Q3
0
VDS
0
0 25 50 75 100 125 150
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and Drain−to−Source
Voltage versus Total Charge
1000
VDD = 1000 V
ID = 14 A
VGS = 10 V
TJ = 25°C
100
td(off)
tr
tf
td(on)
10
0 10
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
15
VGS = 0 V
TJ = 25°C
12
1
9
6
3
0
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the
procedures discussed in AN569, “Transient Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 μs. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) − TC)/(RθJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with
an increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as
shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
http://onsemi.com
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