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NDTL1N60Z 데이터시트 PDF




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부품번호 NDTL1N60Z 기능
기능 N-Channel Power MOSFET / Transistor
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NDTL1N60Z 데이터시트, 핀배열, 회로
NDDL1N60Z, NDTL1N60Z
Product Preview
N-Channel Power MOSFET
600 V, 15 W
Features
100% Avalanche Tested
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
ABSOLUTE MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Symbol NDD NDT Unit
DraintoSource Voltage
CStoenatdinyuSoutasteD, rTaCin=C2u5rr°eCnt(NRoqtJeC 1)
Continuous Drain Current
Steady State, TC = 100°C
R(NqoJCte
1)
Pulsed Drain Current, tp = 10 ms
PStoewaedryDSitsastiep,aTtiCon=–2R5°qCJC
GatetoSource Voltage
Single Pulse DraintoSource
Avalanche Energy (IPK = 1.0 A)
Peak Diode Recovery (Note 2)
VDSS
ID
ID
IDM
PD
VGS
EAS
dv/dt
600
0.8 0.3
V
A
0.5 0.15 A
3.2 1.0
A
25 3 W
±30 V
60 mJ
4.5 V/ns
Source Current (Body Diode)
Lead Temperature for Soldering
Leads
IS
0.5 0.3
A
TL 260 °C
Operating Junction and Storage
Temperature
TJ, TSTG 55 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Limited by maximum junction temperature
2. IS = 1.5 A, di/dt 100 A/ms, VDD BVDSS
THERMAL RESISTANCE
Parameter
Symbol Value Unit
JunctiontoCase (Drain)
NDDL1N60Z
JunctiontoAmbient (Note 4) NDDL1N60Z
(Note 3) NDDL1N60Z1
(Note 4) NDTL1N60Z
(Note 5) NDTL1N60Z
RqJC
RqJA
5 °C/W
50 °C/W
96
62
151
3. Insertion mounted.
4. Surfacemounted on FR4 board using 1” sq. pad size
(Cu area = 1.127” sq. [2 oz] including traces).
5. Surfacemounted on FR4 board using minimum recommended pad size
(Cu area = 0.026” sq. [2 oz]).
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2013
May, 2013 Rev. P1
1
http://onsemi.com
V(BR)DSS
600 V
RDS(ON) MAX
15 W @ 10 V
NChannel MOSFET
D (2)
G (1)
S (3)
MARKING DIAGRAMS
4
Drain
12
3
4 DPAK
CASE 369C
STYLE 2
2
1 Drain 3
4
IPAK
Gate 4 Source
Drain
CASE 369D
STYLE 2
1 23
Y = Year
WW = Work Week
G = PbFree Package
1 23
Gate Drain Source
1 23
A
Y
W
01N60
Drain
4 SOT223
4
CASE 318E
STYLE 3
= Assembly Location
= Year
= Work Week
= Specific Device Code
AYW
L1N60ZG
G
12 3
Gate Drain Source
G = PbFree Package
(*Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Publication Order Number:
NDDL1N60Z/D




NDTL1N60Z pdf, 반도체, 판매, 대치품
NDDL1N60Z, NDTL1N60Z
PACKAGE DIMENSIONS
V
S
T
SEATING
PLANE
B
R
4
123
A
K
IPAK
CASE 369D
ISSUE C
C
E
F
G
J
D 3 PL
0.13 (0.005) M T
H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
INCHES MILLIMETERS
Z
DIM MIN MAX MIN MAX
A 0.235 0.245 5.97 6.35
B 0.250 0.265 6.35 6.73
C 0.086 0.094 2.19 2.38
D 0.027 0.035 0.69 0.88
E 0.018 0.023 0.46 0.58
F 0.037 0.045 0.94 1.14
G 0.090 BSC
2.29 BSC
H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58
K 0.350 0.380 8.89 9.65
R 0.180 0.215 4.45 5.45
S 0.025 0.040 0.63 1.01
V 0.035 0.050 0.89 1.27
Z 0.155 −−− 3.93 −−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
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NDTL1N60Z

N-Channel Power MOSFET / Transistor

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