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LV24250LS 데이터시트 PDF




ON Semiconductor에서 제조한 전자 부품 LV24250LS은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 LV24250LS 자료 제공

부품번호 LV24250LS 기능
기능 1-Chip FM Tuner IC
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LV24250LS 데이터시트, 핀배열, 회로
Ordering number : ENA1699B
LV24250LS
Bi-CMOS LSI
1-Chip FM Tuner IC
for Compact Portable Equipment
http://onsemi.com
Overview
The LV24250LS is an I2C-controlled single-chip FM tuner IC that integrates external components which are necessary
for tuning in a compact VQLP package with dimensions of only 3.5mm×3.5mm.
Features
FM FE
FM IF
MPX stereo decoder
FLL Tuning
Standby
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter
Maximum supply voltage
Maximum input voltage
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VCC max
VDD max
VIN1 max
VIN2 max
Pd max
Topr
Tstg
Conditions
Analog block supply voltage
Digital block supply voltage
SCL, SDA, Int
External_clk_in
Ta 70C *
* : When mounted on the specified printed circuit board (40.0mm × 50.0 mm × 0.8mm), Four layers glass epoxy (2S2P)
Ratings
5.0
4.0
VDD+0.3
VDD+0.3
140
-20 to +70
-40 to +125
Unit
V
V
V
V
mW
C
C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
June, 2013
60811 SY/60910 SY/42810 SY 201003265-S00003 No.A1699-1/18




LV24250LS pdf, 반도체, 판매, 대치품
Block Diagram
LV24250LS
18 17
Line_out_L 19
Package_GND 20
Package_GND 21
Buffer
AMP
FM
Demodulator
16 15 14 13
Line SW
And
Mute
Stereo
Decorder
Voltage
Stabilizer
To
Each Block
De-
emphasis
Package_GND 22
FM Selectivity
Filter
Package_GND 23
RF and FM
Quadrature
Mixer
GND 24
To
Each Block
1
2
FLL Tuning
Quadrature
Oscillator
To
Each
Block
34
Tuning
System
Power
Manage
ment
Digital Interface
I2C Conversion
56
12 Ext_CLK_IN
11 Package_GND
10 Package_GND
9 Package_GND
8 Package_GND
7 SCL
No.A1699-4/18

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LV24250LS 전자부품, 판매, 대치품
LV24250LS
Format of Bus Transfers
Bus transfers are primarily based on the I2C primitives
Start condition
Repeated start condition
Stop condition
Byte write
Byte read
Start, restart, and stop conditions are specified as shown in Table 1 below.
Start
Repeated start
Stop
SCL
SDA
SCL
SDA
SCL
SDA
Fig. 1 the I2C start, repeated start and stop conditions.
For details, like timing, etc., refer to specifications of I2C.
8-bit write
8-bit data is sent from the master microcomputer to LV24250LS.
Data bit consists of MSB first and LSB last.
Data transmission is latched at the rising edge of SCL in synchronization with the SCL clock generated at the master IC.
Do not change data while SCL remains HIGH.
LV24250LS outputs the ACK bit between eighth and ninth falling edges of SCL
SCL
SDA
D7 D6 D5 D4 D3 D2 D1 D0 Ack
Fig. 2 Signal pattern of the I2C byte write
Read is of the same form as write, only except that the data direction is opposite.
Eight data bits are sent from LV24250LS to the master while Ack is sent from the master to LV24250LS.
SCL
SDA
D7 D6 D5 D4 D3 D2 D1 D0 Ack
Fig. 3 Signal pattern of the I2C byte read
The serial clock SCL is supplied from the master side. It is essential that data bit is output from LV24250LS in
synchronization with the falling edge while the master side performs latching at the rising edge.
No.A1699-7/18

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