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6ED003L06-F2 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 6ED003L06-F2
기능 High voltage gate driver IC
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6ED003L06-F2 데이터시트, 핀배열, 회로
EiceDRIVER
High voltage gate driver IC
6ED family - 2nd generation
3 phase 600 V gate drive IC
6ED003L06-F2
6ED003L02-F2
EiceDRIVER
datasheet
<Revision 2.8>, 05.08.2016
Industrial Power Control




6ED003L06-F2 pdf, 반도체, 판매, 대치품
EiceDRIVER™
6ED003L06-F2, 6ED003L02-F2
Table of Contents
1 Overview .............................................................................................................................................5
2 Blockdiagram......................................................................................................................................6
3 Pin configuration, description, and functionality ...........................................................................7
3.1 Low Side and High Side Control Pins (Pin 2, 3, 4, 5, 6, 7) ..................................................................7
3.2 EN (Gate Driver Enable, Pin 10) ..........................................................................................................8
3.3 /FAULT (Fault Feedback, Pin 8) ..........................................................................................................8
3.4 ITRIP and RCIN (Over-Current Detection Function, Pin 9, 11) ...........................................................9
3.5 VCC, VSS and COM (Low Side Supply, Pin 1, 12,13) ........................................................................9
3.6 VB1,2,3 and VS1,2,3 (High Side Supplies, Pin 18, 20, 22, 24, 26, 28) ...............................................9
3.7 LO1,2,3 and HO1,2,3 (Low and High Side Outputs, Pin 14, 15, 16, 19, 23, 27) .................................9
4 Electrical Parameters.......................................................................................................................10
4.1 Absolute Maximum Ratings ...............................................................................................................10
4.2 Required operation conditions ...........................................................................................................11
4.3 Operating Range ................................................................................................................................11
4.4 Static logic function table ...................................................................................................................12
4.5 Static parameters ...............................................................................................................................12
4.6 Dynamic parameters ..........................................................................................................................14
5 Timing diagrams...............................................................................................................................15
6 Package.............................................................................................................................................18
6.1 PG-DSO-28 ........................................................................................................................................18
6.2 PG-TSSOP-28....................................................................................................................................19
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Typical Application ...............................................................................................................................6
Block diagram for 6ED003L06-F2 / 6ED003L02-F2 ............................................................................6
Pin Configuration of 6ED003L06-F2 and 6ED003L02-F2 ...................................................................7
Input pin structure.................................................................................................................................7
Input filter timing diagram .....................................................................................................................8
EN pin structures..................................................................................................................................8
/FAULT pin structures ..........................................................................................................................8
Timing of short pulse suppression .....................................................................................................15
Timing of internal deadtime................................................................................................................15
Enable delay time definition ...............................................................................................................15
Input to output propagation delay times and switching times definition .............................................16
Operating areas..................................................................................................................................16
ITRIP-Timing ......................................................................................................................................16
ITRIP input filter time..........................................................................................................................17
Package drawing................................................................................................................................18
PCB reference layout .........................................................................................................................18
Package drawing................................................................................................................................19
PCB reference layout (according to JEDEC 1s0P) left: Reference layout right: detail of footprint19
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Members of 6ED family 2nd generation .............................................................................................5
Pin Description .....................................................................................................................................7
Abs. maximum ratings........................................................................................................................10
Required Operation Conditions..........................................................................................................11
Operating range .................................................................................................................................11
Static parameters ...............................................................................................................................12
Dynamic parameters ..........................................................................................................................14
Data of reference layout .....................................................................................................................19
datasheet
4 <Revision 2.8>, 05.08.2016

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6ED003L06-F2 전자부품, 판매, 대치품
EiceDRIVER™
6ED003L06-F2, 6ED003L02-F2
3 Pin configuration, description, and functionality
1 VCC
2 HIN1
3 HIN2
4 HIN3
5 LIN1
6 LIN2
7 LIN3
8 FAULT
9 ITRIP
10 EN
11 RCIN
12 VSS
13 COM
14 LO3
VB1 28
HO1 27
VS1 26
nc 25
VB2 24
HO2 23
VS2 22
nc 21
VB3 20
HO3 19
VS3 18
nc 17
LO1 16
LO2 15
Figure 3 Pin Configuration of 6ED003L06-F2 and 6ED003L02-F2
Table 2
Symbol
VCC
VSS
/HIN1,2,3
/LIN1,2,3
/FAULT
EN
ITRIP
RCIN
COM
VB1,2,3
HO1,2,3
VS1,2,3
LO1,2,3
nc
Pin Description
Description
Low side power supply
Logic ground
High side logic input
Low side logic input
Indicates over-current and under-voltage (negative logic, open-drain output)
Enable I/O functionality (positive logic)
Analog input for over-current shut down, activates FAULT and RCIN to VSS
External RC-network to define FAULT clear delay after FAULT-Signal (TFLTCLR)
Low side gate driver reference
High side positive power supply
High side gate driver output
High side negative power supply
Low side gate driver output
Not connected
3.1 Low Side and High Side Control Pins (Pin 2, 3, 4, 5, 6, 7)
The Schmitt trigger input threshold of them are such to guarantee LSTTL and CMOS compatibility down to 3.3 V
controller outputs. Input Schmitt trigger and noise filter provide beneficial noise rejection to short input pulses
according to Figure 4 and Figure 5.
HINx
LINx
Vcc
Schmitt-Trigger
UZ=10.5V
SWITCH LEVEL
VIH; VIL
INPUT NOISE
FILTER
Figure 4 Input pin structure
datasheet
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전력 반도체 판매 ( IGBT, TR 모듈, SCR, 다이오드 모듈 )

휴대전화 : 010-3582-2743


상호 : 아이지 인터내셔날

전화번호 : 051-319-2877, [ 홈페이지 ]



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6ED003L06-F2

High voltage gate driver IC

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