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PDF F25L02PA Data sheet ( Hoja de datos )
| Número de pieza | F25L02PA | |
| Descripción | 3V Only 2 Mbit Serial Flash Memory | |
| Fabricantes | Elite Semiconductor | |
| Logotipo |  |
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ESMT
Flash
FEATURES
y Single supply voltage 2.7~3.6V
y Standard, Dual SPI
y Speed
- Read max frequency: 33MHz
- Fast Read max frequency: 50MHz; 86MHz; 100MHz
- Fast Read Dual max frequency: 50MHz / 86MHz/ 100MHz
(100MHz / 172MHz/ 200MHz equivalent Dual SPI)
y Low power consumption
- Active current: 25 mA
- Standby current: 30 μ A
- Deep Power Down current: 5 μ A
y Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
y Program
- Page programming time: 1.5 ms (typical)
F25L02PA
3V Only 2 Mbit Serial Flash Memory
with Dual Output
y Erase
- Chip erase time 2 sec (typical)
- Block erase time 0.75 sec (typical)
- Sector erase time 150 ms (typical)
y Page Programming
- 256 byte per programmable page
y SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
y End of program or erase detection
y Write Protect ( WP )
y Hold Pin ( HOLD )
y All Pb-free products are RoHS-Compliant
ORDERING INFORMATION
Product ID
F25L02PA –50PG
F25L02PA –86PG
F25L02PA –100PG
F25L02PA –50PAG
F25L02PA –86PAG
F25L02PA –100PAG
F25L02PA –50DG
F25L02PA –86DG
F25L02PA –100DG
F25L02PA –50HG
F25L02PA –86HG
F25L02PA –100HG
F25L02PA –50UG
F25L02PA –86UG
F25L02PA –100UG
Speed
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
Package
Comments
8-lead
SOIC
150 mil
Pb-free
8-lead
SOIC
200 mil
Pb-free
8-pin
PDIP
300 mil
Pb-free
8-contact
WSON
6x5 mm
Pb-free
8-contact
USON
2x3 mm
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2013
Revision: 1.2
1/35
1 page  
ESMT
FUNCTIONAL BLOCK DIAGRAM
F25L02PA
Address
Buffers
and
Latches
X-Decoder
Control Logic
Flash
Y-Decoder
I/O Butters
and
Data Latches
Serial Interface
CE SCK SI SO WP HOLD
SECTOR STRUCTURE
Block
3
2
1
0
Table 1: F25L02PA Sector Address Table
Sector
63
:
48
47
:
32
31
:
16
15
:
0
Sector Size
(Kbytes)
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
Address range
03F000H – 03FFFFH
:
030000H – 030FFFH
02F000H – 02FFFFH
:
020000H – 020FFFH
01F000H – 01FFFFH
:
010000H – 010FFFH
00F000H – 00FFFFH
:
000000H – 000FFFH
Block Address
A17 A16
11
10
01
00
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2013
Revision: 1.2
5/35
5 Page 
ESMT
F25L02PA
Read (33MHz)
The Read instruction supports up to 33 MHz, it outputs the data
starting from the specified address location. The data output
stream is continuous through all addresses until terminated by a
low to high transition on CE . The internal address pointer will
automatically increment until the highest memory address is
reached. Once the highest memory address is reached, the
address pointer will automatically increment to the beginning
(wrap-around) of the address space, i.e. for 2Mbit density, once
the data from address location 03FFFFH had been read, the next
output will be from address location 000000H.
The Read instruction is initiated by executing an 8-bit command,
03H, followed by address bits [A23 -A0]. CE must remain active
low for the duration of the Read cycle. See Figure 2 for the Read
sequence.
Figure 2: Read Sequence
Fast Read (50 MHz ~ 100 MHz)
The Fast Read instruction supporting up to 100 MHz is initiated
by executing an 8-bit command, 0BH, followed by address bits
[A23 -A0] and a dummy byte. CE must remain active low for the
duration of the Fast Read cycle. See Figure 3 for the Fast Read
sequence.
Following a dummy byte (8 clocks input dummy cycle), the Fast
Read instruction outputs the data starting from the specified
address location. The data output stream is continuous through
all addresses until terminated by a low to high transition on CE .
The internal address pointer will automatically increment until the
highest memory address is reached. Once the highest memory
address is reached, the address pointer will automatically
increment to the beginning (wrap-around) of the address space,
i.e. for 2Mbit density, once the data from address location
03FFFFH has been read, the next output will be from address
location 000000H.
CE
MODE3
SCK MODE0
0 12 3 45 67 8
15 16 23 24
31 32 39 40 47 48 55 56 63 64 71 72
80
SI
0B
ADD.
ADD.
A DD.
MSB
MSB
SO HIGH IMPENANCE
Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH)
Figure 3: Fast Read Sequence
Elite Semiconductor Memory Technology Inc.
X
N
D OU T
MSB
N+1
DOUT
N+2
DOUT
N+3
D OU T
N+4
D OU T
Publication Date: Mar. 2013
Revision: 1.2
11/35
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet F25L02PA.PDF ] | |
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