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PDF MGA-13516 Data sheet ( Hoja de datos )
| Número de pieza | MGA-13516 | |
| Descripción | Low Noise Amplifier | |
| Fabricantes | AVAGO | |
| Logotipo |  |
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MGA-13516
High Gain, High Linearity, Active Bias,
Low Noise Amplifier
Data Sheet
Description
Avago Technologies’ MGA-13516 is a two stage, easy-to-
use GaAs MMIC Low Noise Amplifier (LNA) with active bias.
The LNA has low noise with good input return loss and
high linearity achieved through the use of Avago Tech-
nologies’ proprietary 0.5um and 0.25um GaAs Enhance-
ment-mode pHEMT process. Both LNAs inside have extra
feature that allows a designer to adjust supply current.
The first stage has an additional feature where the gain
can be adjusted externally without affecting noise figure.
Minimum matching needed for input, output and the
inter-stage between the two LNA.
It is designed for optimum use between 400MHz to
1.5GHz. For optimum performance at higher frequency
from 1.4GHz to 2.7GHz, the MGA-14516 is recommended.
Both MGA-13516 & MGA-14516 share the same package
and pinout.
Pin Configuration and Package Marking
4.0 x 4.0 x 0.85 mm3 16-lead QFN
13516
YYWW
XXXX
Pin 12
Pin 11
Pin 10
Pin 9
Pin 1
Pin 2
Pin 3
Pin 4
Features
• Low noise figure
• High gain
• Good IRL
• High linearity performance
• High reverse isolation
• Externally adjustable supply current
• Externally adjustable gain
• GaAs E-pHEMT Technology [1]
• Low cost QFN package
• Excellent uniformity in product specifications
Specifications
900MHz ; Q1 : 5V, 45mA (typ) Q2 : 5V, 110mA
• 31.8 dB Gain
• 0.66 dB Noise Figure
• 13 dB IRL
• 38 dBm Output IP3
• 23.5 dBm Output Power at 1dB gain compression
Applications
• Low noise amplifier for cellular infrastructure including
GSM, CDMA and W-CDMA.
• Other very low noise applications.
TOP VIEW
[1]
[2]
[3]
[4]
BOTTOM VIEW
Pin Description Pin Description
1 Not Used 9 Not Used
[12] 2 NC
10 RFout
[11] 3 RFin
11 RFout
[10] 4 RFgnd1
[9]
5 Vbias1
6 FB1
12 Not Used
13 Vg
14 RFgnd2
7 RFout1
15 Vm
8 RFin2
16 Vbias
Note:
1. Enhancement mode technology employs positive Vgs, thereby
eliminating the need of negative gate voltage associated with
conventional depletion mode devices.
Attention: Observe precautions for
handling electrostatic sensitive devices
ESD Machine Model = 40 V
ESD Human Body Model = 200 V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.
Notes:
Package marking provides orientation and identification “13516” is the
Product Identification, “YYWW” is the Date Code, “XXXX” is the last 4
digits of the lot number.
1 page  
MGA-13516 Typical Performance
TA = 25°C, Vdd1=5V, Vdd2=5V, Vbias=5V unless stated otherwise. Measured on demo board in Fig. 5 with component
list in Table 1 for 900MHz matching.
60 140
50 120
40 100
80
30
60
20 40
10 20
0
-60 -40 -20 0 20 40 60 80 100
Temperature (°C)
Figure 7. Idd1 vs. Temperature
0
-60 -40 -20
0 20 40 60
Temperature (°C)
80 100
Figure 8. Idd2 vs. Temperature
6
5
4
3
2
1
0
-60 -40 -20 0 20 40 60 80 100
Temperature (°C)
Figure 9. Ibias vs. Temperature
5 Page 
PCB Land Pattern and Stencil Design
0.650
0.650
0.300 0.270
2.200
0.650
2.200 0.350
PCB Land Pattern (Top View)
0.485
0.650
0.300
0.270
2.200
1.980
2.200
1.980
0.485
Combines PCB & Stencil Layouts
All Dimension are in millimeters
1.980
Stencil Outline
1.980
0.492
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet MGA-13516.PDF ] | |
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