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부품번호 W968D6DA 기능
기능 CellularRAM
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W968D6DA 데이터시트, 핀배열, 회로
W968D6DA
256Mb Async./Page,Syn./Burst CellularRAM
1. GENERAL DESCRIPTION
Winbond CellularRAM™ products are high-speed, CMOS pseudo-static random access memories developed for
low-power, portable applications. The device has a DRAM core organized. These devices include an industry-
standard burst mode Flash interface that dramatically increases read/write bandwidth compared with other low-
power SRAM or Pseudo SRAM offerings.
To operate seamlessly on a burst Flash bus, CellularRAM products incorporate a transparent self refresh
mechanism. The hidden refresh requires no additional support from the system memory controller and has no
significant impact on device READ/WRITE performance.
Two user-accessible control registers define device operation. The Bus Configuration Register (BCR) defines how
the CellularRAM device interacts with the system memory bus and is nearly identical to its counterpart on burst
mode Flash devices. The Refresh Configuration Register (RCR) is used to control how refresh is performed on the
DRAM array. These registers are automatically loaded with default settings during power-up and can be updated
anytime during normal operation.
Special attention has been focused on standby current consumption during self refresh. CellularRAM products
include three mechanisms to minimize standby current. Partial array refresh (PAR) enables the system to limit
refresh to only that part of the DRAM array that contains essential data. Temperature compensated refresh (TCR)
uses an on-chip sensor to adjust the refresh rate to match the device temperaturethe refresh rate decreases at
lower temperatures to minimize current consumption during standby. Deep power-down (DPD) enables the system
to halt the refresh operation altogether when no vital information is stored in the device. The system configurable
refresh mechanisms are accessed through the RCR.
This CellularRAM device is compliant with the industry-standard CellularRAM 1.5 generation feature set established
by the CellularRAM Workgroup. It includes support for both variable and fixed latency, with 3 output-device drive-
strength settings, additional wrap options, and a device ID register (DIDR).
2. FEATURES
•Supports asynchronous, page, and burst operations
• VCC, VCCQ Voltages:
1.7V1.95V VCC
1.7V1.95V VCCQ
• Random access time: 70ns
• Burst mode READ and WRITE access:
Configuration:
256Mb 16Mx16
Vcc core voltage supply: 1.8V
VccQ I/O voltage supply: 1.8V
Package: 54 Ball VFBGA
4, 8, 16, or 32 words, or continuous burst
Active current (ICC1) <25mA at 85°C
Burst wrap or sequential
Max clock rate: 133 MHz (tCLK = 7.5ns)
• Page mode READ access:
Sixteen-word page size
Interpage READ access: 70ns
Standby current 400μA (max) at 85°C
Deep power-down: Typical 25μA
Operating temperature range: -40°C ~ 85°C
Intrapage READ access: 20ns
• Low-power features
On-chip temperature compensated refresh (TCR)
Partial array refresh (PAR)
Deep power-down (DPD) mode
Publication Release Date : June 27, 2013
- 1 - Revision : A01-003




W968D6DA pdf, 반도체, 판매, 대치품
W968D6DA
256Mb Async./Page,Syn./Burst CellularRAM
8.4.3.10 WAIT Configuration During Burst Operation ......................................................................................................... 30
8.4.3.11 WAIT Function by Configuration (WC) Lat=2, WP=0 ......................................................................................... 30
8.4.3.12 Latency Counter (BCR[13:11]) .............................................................................................................................. 31
8.4.3.13 Initial Access Latency (BCR[14])........................................................................................................................... 31
8.4.3.14 Allowed Latency Counter Settings in Variable Latency Mode ............................................................................... 31
8.4.3.15 Latency Counter (Variable Initial Latency, No Refresh Collision) .......................................................................... 32
8.4.3.16 Latency Counter (Variable Initial Latency, With Refresh Collision) ....................................................................... 32
8.4.3.17 Allowed Latency Counter Settings in Fixed Latency Mode ................................................................................... 33
8.4.3.18 Latency Counter (Fixed Latency) .......................................................................................................................... 33
8.4.3.19 Burst Write Always Produces Fixed Latency......................................................................................................... 34
8.4.3.20 Burst Interrupt ....................................................................................................................................................... 34
8.4.3.21 End-of-Row Condition ........................................................................................................................................... 34
8.4.3.22 Burst Termination or Burst Interrupt At the End of Row ........................................................................................ 34
8.4.3.23 Operating Mode (BCR[15]).................................................................................................................................... 34
8.4.4 Refresh Configuration Register .................................................................................................................... 35
8.4.4.1 Refresh Configuration Register Mapping ................................................................................................................ 35
8.4.4.2 Partial Array Refresh (RCR[2:0] Default = Full Array Refresh ................................................................................. 35
8.4.4.3 Address Patterns for PAR (RCR[4] = 1) .................................................................................................................. 36
8.4.4.4 Deep Power-Down (RCR[4]) ................................................................................................................................... 36
8.4.4.5 Page Mode Operation (RCR[7]) .............................................................................................................................. 36
8.4.5 Device Identification Register ....................................................................................................................... 36
8.4.5.1 Device Identification Register Mapping ................................................................................................................... 36
8.4.6 Virtual Chip Enable Function: ....................................................................................................................... 36
9. ELECTRICAL CHARACTERISTIC ......................................................................................... 37
9.1 Absolute Maximum DC, AC Ratings ..................................................................................................37
9.2 Electrical Characteristics and Operating Conditions ..........................................................................38
9.3 Deep Power-Down Specifications......................................................................................................39
9.4 Partial Array Self Refresh Standby Current .......................................................................................39
9.5 Capacitance .......................................................................................................................................39
9.6 AC Input-Output Reference Waveform ..............................................................................................39
9.7 AC Output Load Circuit ......................................................................................................................39
10. TIMING REQUIRMENTS ....................................................................................................... 40
10.1 Read, Write Timing Requirements ...................................................................................................40
10.1.1 Asynchronous READ Cycle Timing Requirements..................................................................................... 40
10.1.2 Burst READ Cycle Timing Requirements ................................................................................................... 41
10.1.3 Asynchronous WRITE Cycle Timing Requirements ................................................................................... 42
10.1.4 Burst WRITE Cycle Timing Requirements.................................................................................................. 43
10.2 TIMING DIAGRAMS ........................................................................................................................44
10.2.1 Initialization Period...................................................................................................................................... 44
10.2.2 DPD Entry and Exit Timing Parameters ..................................................................................................... 44
10.2.3 Initialization and DPD Timing Parameters .................................................................................................. 44
10.2.4 Asynchronous READ .................................................................................................................................. 45
10.2.5 Asynchronous READ Using ADV# ............................................................................................................. 46
10.2.6 Page Mode READ....................................................................................................................................... 47
10.2.7 Single-Access Burst READ Operation-Variable Latency............................................................................ 48
10.2.8 4-Word Burst READ Operation-Variable Latency....................................................................................... 49
10.2.9 Single-Access Burst READ Operation-Fixed Latency ................................................................................ 50
10.2.10 4-Word Burst READ Operation-Fixed Latency ......................................................................................... 51
10.2.11 READ Burst Suspend ............................................................................................................................... 52
10.2.12 Burst READ at End-of-Row (Wrap Off)..................................................................................................... 53
10.2.13 Burst READ Row Boundary Crossing....................................................................................................... 54
10.2.14 CE#-Controlled Asynchronous WRITE..................................................................................................... 55
10.2.15 LB# / UB# Controlled Asynchronous WRITE............................................................................................ 56
10.2.16 WE# - Controlled Asynchronous WRITE .................................................................................................. 57
10.2.17 Asynchronous WRITE Using ADV#.......................................................................................................... 58
10.2.18 Burst WRITE Operation-Variable Latency Mode ...................................................................................... 59
10.2.19 Burst WRITE Operation-Fixed Latency Mode .......................................................................................... 60
Publication Release Date : June 27, 2013
- 4 - Revision : A01-003

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W968D6DA 전자부품, 판매, 대치품
W968D6DA
5. Pin Description
5.1 Signal Description
256Mb Async./Page,Syn./Burst CellularRAM
Symbol Type
Description
A[max:0]
Input
Address inputs: Inputs for addresses during READ and WRITE operations.
Addresses are internally latched during READ and WRITE cycles. The address
lines are also used to define the value to be loaded into the BCR or the RCR.
A[max:0] is A[23:0] for 256Mb.
CLK
(Note 1)
Input
Clock: Synchronizes the memory to the system operating frequency during
synchronous operations. When configured for synchronous operation, the
address is latched on the first rising CLK edge when ADV# is active. CLK is
static LOW during asynchronous access READ and WRITE operations and
during PAGE READ ACCESS operations.
ADV#
(Note 1)
CRE
CE#
Input
Input
Input
Address valid: Indicates that a valid address is present on the address inputs.
In asynchronous mode, addresses can be latched on the rising edge of ADV#
or ADV# can be held LOW. In synchronous mode, addresses are latched on the 1st rising
clock edge while ADV# is low. In synchronous mode, the ADV# low pulse width is 1 clock
cycle.
Control register enable: When CRE is HIGH, WRITE operations load the RCR
or BCR, and READ operations access the RCR, BCR, or DIDR.
Chip enable: Activates the device when LOW. When CE# is HIGH, the device
is disabled and goes into standby or deep power-down mode.
OE#
WE#
LB#
Input
Input
Input
Output enable: Enables the output buffers when LOW. When OE# is HIGH,
the output buffers are disabled.
Write enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW,
the cycle is a WRITE to either a configuration register or to the memory array.
Lower byte enable. DQ[7:0] .
UB# Input Upper byte enable. DQ[15:8] .
DQ[15:0] Input/Output Data inputs/outputs.
WAIT
(Note 1)
NC
Output
Wait: Provides data-valid feedback during burst READ and WRITE
operations. The signal is gated by CE#. WAIT is used to arbitrate collisions
between refresh and READ/WRITE operations. WAIT is also asserted at the
end of a row unless wrapping within the burst length. WAIT is asserted and
should be ignored during asynchronous and page mode operations. WAIT is
High-Z when CE# is HIGH.
No internal electrical connection is present.
VCC
Supply Device power supply: power supply for device core operation.
VCCQ
Supply I/O power supply: power supply for input/output buffers.
VSS
Supply VSS must be connected to ground.
VSSQ
Supply VSSQ must be connected to ground.
Note: 1. When using asynchronous mode or page mode exclusively, the CLK and ADV# inputs can be tied to VSS. WAIT will be
asserted but should be ignored during asynchronous and page mode operations.
Publication Release Date : June 27, 2013
- 7 - Revision : A01-003

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부품번호상세설명 및 기능제조사
W968D6DA

CellularRAM

Winbond
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