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W94AD6KB 데이터시트 PDF




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기능 1Gb Mobile LPDDR
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W94AD6KB 데이터시트, 핀배열, 회로
W94AD6KB / W94AD2KB
1Gb Mobile LPDDR
Table of Contents-
1. GENERAL DESCRIPTION .................................................................................................................................4
2. FEATURES ........................................................................................................................................................4
3. ORDER INFORMATION ....................................................................................................................................5
4. BALL CONFIGURATION....................................................................................................................................6
4.1 Ball Assignment: LPDDR x16 ...............................................................................................................6
4.2 Ball Assignment: LPDDR x32 ...............................................................................................................6
5. BALL DESCRIPTION .........................................................................................................................................7
5.1 Signal Descriptions...............................................................................................................................7
5.2 Addressing Table..................................................................................................................................8
6. BLOCK DIAGRAM..............................................................................................................................................9
6.1 Block Diagram ......................................................................................................................................9
6.2 Simplified State Diagram ....................................................................................................................10
7. FUNCTIONAL DESCRIPTION .........................................................................................................................11
7.1 Initialization.........................................................................................................................................11
7.1.1 Initialization Flow Diagram....................................................................................................12
7.1.2 Initialization Waveform Sequence ........................................................................................13
7.2 Mode Register Set Operation .............................................................................................................13
7.3 Mode Register Definition ....................................................................................................................14
7.3.1 Burst Length .........................................................................................................................14
7.3.2 Burst Definition .....................................................................................................................15
7.3.3 Burst Type ............................................................................................................................16
7.3.4 Read Latency .......................................................................................................................16
7.4 Extended Mode Register Description .................................................................................................16
7.4.1 Extended Mode Register Definition ......................................................................................17
7.4.2 Partial Array Self Refresh .....................................................................................................17
7.4.3 Automatic Temperature Compensated Self Refresh ............................................................17
7.4.4 Output Drive Strength...........................................................................................................17
7.5 Status Register Read .........................................................................................................................18
7.5.1 SRR Register Definition........................................................................................................18
7.5.2 Status Register Read Timing Diagram .................................................................................19
7.6 Commands .........................................................................................................................................20
7.6.1 Basic Timing Parameters for Commands .............................................................................20
7.6.2 Truth Table Commands..................................................................................................20
7.6.3 Truth Table - DM Operations................................................................................................21
7.6.4 Truth Table CKE.............................................................................................................21
7.6.5 Truth Table - Current State Bank n - Command to Bank n...................................................22
7.6.6 Truth Table - Current State Bank n, Command to Bank m ...................................................23
8. OPERATION ....................................................................................................................................................25
8.1 Deselect .............................................................................................................................................25
8.2 No Operation ......................................................................................................................................25
8.2.1 NOP Command ....................................................................................................................25
8.3 Mode Register Set..............................................................................................................................26
8.3.1 Mode Register Set Command ..............................................................................................26
8.3.2 Mode Register Set Command Timing...................................................................................26
Publication Release Date: Oct. 02, 2014
Revision: A01-005
-1-




W94AD6KB pdf, 반도체, 판매, 대치품
W94AD6KB / W94AD2KB
1. GENERAL DESCRIPTION
W94AD6KB / W94AD2KB is a high-speed Low Power double data rate synchronous dynamic random
access memory (LPDDR SDRAM), An access to the LPDDR SDRAM is burst oriented. Consecutive
memory location in one page can be accessed at a burst length of 2, 4, 8 and 16 when a bank and
row is selected by an ACTIVE command. Column addresses are automatically generated by the
LPDDR SDRAM internal counter in burst operation. Random column read is also possible by providing
its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to
hide the pre-charging time. By setting programmable Mode Registers, the system can change burst
length, latency cycle, interleave or sequential burst to maximize its performance. The device supports
special low power functions such as Partial Array Self Refresh (PASR) and Automatic Temperature
Compensated Self Refresh (ATCSR).
2. FEATURES
VDD = 1.7~1.95V
VDDQ = 1.7~1.95V
Data width: x16 / x32
Clock rate: 200MHz (-5),166MHz (-6)
Standard Self Refresh Mode
Partial Array Self-Refresh(PASR)
Auto Temperature Compensated Self Refresh
(ATCSR)
Power Down Mode
Deep Power Down Mode (DPD Mode)
Programmable output buffer driver strength
Four internal banks for concurrent operation
Data mask (DM) for write data
Clock Stop capability during idle periods
Auto Pre-charge option for each burst access
Double data rate for data output
Differential clock inputs (CK and CK )
Bidirectional, data strobe (DQS)
CAS Latency: 2 and 3
Burst Length: 2, 4, 8 and 16
Burst Type: Sequential or Interleave
64 ms Refresh period
Interface: LVCMOS compatible
Support package:
60 balls VFBGA (x16)
90 balls VFBGA (x32)
Operating Temperature Range
Extended: -25°C ~ +85°C
Industrial: -40°C ~ +85°C
Publication Release Date: Oct. 02, 2014
Revision: A01-005
-4-

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W94AD6KB 전자부품, 판매, 대치품
W94AD6KB / W94AD2KB
5. BALL DESCRIPTION
5.1 Signal Descriptions
SIGNAL NAME
A [n:0]
BA0, BA1
DQ0~DQ15 (×16)
DQ0~DQ31 (×32)
TYPE
Input
Input
I/O
FUNCTION
Address
Bank Select
Data Input/
Output
DESCRIPTION
Provide the row address for ACTIVE commands, and
the column address and AUTO PRECHARGE bit for
READ/WRITE commands, to select one location out of
the memory array in the respective bank. The address
inputs also provide the opcode during a MODE
REGISTER SET command.
A10 is used for Auto Pre-charge Select.
Define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
Data bus: Input / Output.
CS enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are
CS Input Chip Select masked when CS is registered HIGH. CS provides
for external bank selection on systems with multiple
banks. CS is considered part of the command code.
RAS
CAS
Input
Input
Row Address
Strobe
Column
Address
Strobe
RAS , CAS and WE (along with CS ) define the
command being entered.
Referred to RAS .
WE
UDM, LDM (x16);
DM0 to DM3 (x32)
Input
Input
Write Enable
Input Mask
Referred to RAS .
Input Data Mask: DM is an input mask signal for write
data. Input data is masked when DM is sampled HIGH
along with that input data during a WRITE access. DM
is sampled on both edges of DQS. Although DM pins
are input-only, the DM loading matches the DQ and
DQS loading.
x16: LDM: DQ0 - DQ7, UDM: DQ8 DQ15
x32: DM0: DQ0 - DQ7, DM1: DQ8 DQ15,
DM2: DQ16 DQ23, DM3: DQ24 DQ31.
CK / CK
Input
Clock Inputs
CK and CK are differential clock inputs. All address
and control input signals are sampled on the crossing of
the positive edge of CK and negative edge of CK .Input
and output data is referenced to the crossing of CK and
CK (both directions of crossing). Internal clock signals
are derived from CK/ CK .
Publication Release Date: Oct. 02, 2014
Revision: A01-005
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W94AD6KB

1Gb Mobile LPDDR

Winbond
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