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부품번호 | PESD5V0U5BF 기능 |
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기능 | Ultra low capacitance bidirectional fivefold ESD protection arrays | ||
제조업체 | NXP Semiconductors | ||
로고 | |||
전체 12 페이지수
PESD5V0U5BF; PESD5V0U5BV
Ultra low capacitance bidirectional fivefold ESD
protection arrays
Rev. 01 — 15 August 2008
Product data sheet
1. Product profile
1.1 General description
Ultra low capacitance bidirectional fivefold ElectroStatic Discharge (ESD) protection
arrays in ultra small Surface-Mounted Device (SMD) plastic packages designed to protect
up to five signal lines from the damage caused by ESD and other transients.
Table 1. Product overview
Type number
Package
NXP
PESD5V0U5BF
SOT886
PESD5V0U5BV
SOT666
JEDEC
MO-252
-
Package configuration
leadless ultra small
ultra small and flat lead
1.2 Features
I Bidirectional ESD protection of up to I ESD protection up to 10 kV
five lines
I Ultra low diode capacitance: Cd = 2.9 pF I IEC 61000-4-2; level 4 (ESD)
I Ultra low leakage current: IRM = 5 nA I AEC-Q101 qualified
1.3 Applications
I Computers and peripherals
I Audio and video equipment
I Cellular handsets and accessories
I 10/100/1000 Mbit/s Ethernet
I Communication systems
I Portable electronics
I Subscriber Identity Module (SIM) card
protection
I FireWire
I High-speed data lines
NXP Semiconductors
PESD5V0U5BF; PESD5V0U5BV
Ultra low capacitance bidirectional fivefold ESD protection arrays
Table 8. ESD standards compliance
Standard
Per diode
IEC 61000-4-2; level 4 (ESD)
MIL-STD-883; class 3 (human body model)
Conditions
> 15 kV (air); > 8 kV (contact)
> 4 kV
IPP
100 %
90 %
001aaa631
10 %
tr = 0.7 ns to 1 ns
30 ns
60 ns
Fig 1. ESD pulse waveform according to IEC 61000-4-2
t
PESD5V0U5BF_PESD5V0U5BV_1
Product data sheet
Rev. 01 — 15 August 2008
© NXP B.V. 2008. All rights reserved.
4 of 12
4페이지 NXP Semiconductors
PESD5V0U5BF; PESD5V0U5BV
Ultra low capacitance bidirectional fivefold ESD protection arrays
7. Application information
The PESD5V0U5BF and the PESD5V0U5BV are designed for the protection of up to five
bidirectional data or signal lines from the damage caused by ESD and surge pulses. The
devices may be used on lines where the signal polarities are both, positive and negative
with respect to ground.
data- or transmission lines
DUT
16
25
34
006aab347
Fig 5. Application diagram
Circuit board layout and protection device placement
Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT)
and surge transients. The following guidelines are recommended:
1. Place the device as close to the input terminal or connector as possible.
2. The path length between the device and the protected line should be minimized.
3. Keep parallel signal paths to a minimum.
4. Avoid running protected conductors in parallel with unprotected conductors.
5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and
ground loops.
6. Minimize the length of the transient return path to ground.
7. Avoid using shared transient return paths to a common ground point.
8. Ground planes should be used whenever possible. For multilayer PCBs, use ground
vias.
8. Test information
8.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is
suitable for use in automotive applications.
PESD5V0U5BF_PESD5V0U5BV_1
Product data sheet
Rev. 01 — 15 August 2008
© NXP B.V. 2008. All rights reserved.
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부품번호 | 상세설명 및 기능 | 제조사 |
PESD5V0U5BF | Ultra low capacitance bidirectional fivefold ESD protection arrays | NXP Semiconductors |
PESD5V0U5BV | Ultra low capacitance bidirectional fivefold ESD protection arrays | NXP Semiconductors |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |