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부품번호 PCU9661 기능
기능 Parallel bus to 1 channel UFm I2C-bus controller
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PCU9661 데이터시트, 핀배열, 회로
PCU9661
Parallel bus to 1 channel UFm I2C-bus controller
Rev. 1 — 12 September 2011
Product data sheet
1. General description
The PCU9661 is an advanced single master mode I2C-bus controller. It is a fourth
generation bus controller designed for data intensive I2C-bus data transfers. It has a
transmit only transfer rate of up to 5 Mbits/s using the new Ultra Fast-mode (UFm) bus
with push-pull topology. The serial channel has a generous 4352 byte data buffer which
makes the PCU9661 the ideal companion to any CPU that needs to transmit and receive
large amounts of serial data with minimal interruptions.
The PCU9661 is an 8-bit parallel-bus to I2C-bus protocol converter. It can be configured to
communicate with up to 64 slaves in one serial sequence with no intervention from the
CPU. The controller also has a sequence loop control feature that allows it to
automatically retransmit a stored sequence.
Its onboard oscillator and PLL allow the controller to generate the clocks for the I2C-bus
and for the interval timer used in sequence looping. This feature greatly reduces CPU
overhead when data refresh is required in fault tolerant applications.
An external trigger input allows data synchronization with external events. The trigger
signal controls the rate at which a stored sequence is re-transmitted over the I2C-bus.
Error reporting is handled at the transaction level, channel level, and controller level.
A simple interrupt tree and interrupt masks allow further customization of interrupt
management.
The controller parallel bus interface runs at 3.3 V and the I2C-bus I/Os logic levels are
referenced to a dedicated VDD(IO) input pin with a range of 3.0 V to 5.5 V.
2. Features and benefits
Parallel-bus to I2C-bus protocol converter and interface
5 Mbit/s unidirectional data transfer Ultra Fast-mode (UFm) channel (push-pull driver)
Internal oscillator trimmed to 1 % accuracy reduces external components
4352-byte UFm channel buffer
Three levels of reset: software channel reset, global software reset on parallel bus,
global hardware RESET pin
Communicates with up to 64 slaves in one serial sequence
Sequence looping with interval timer
JTAG port available for boundary scan testing during board manufacturing process
Trigger input synchronizes serial communication exactly with external events
Maskable interrupts
Operating supply voltage: 3.0 V to 3.6 V (device and host interface)




PCU9661 pdf, 반도체, 판매, 대치품
NXP Semiconductors
6. Pinning information
6.1 Pinning
PCU9661
Parallel bus to 1 channel UFm I2C-bus controller
D6 1
D7 2
A0 3
A1 4
A2 5
A3 6
VDD
VSS
A4
7
8
9
A5 10
A6 11
A7 12
PCU9661B
36 RESET
35 VSS
34 TRIG
33 CE
32 RD
31 WR
30 VDD
29 VSS
28 n.c.
27 n.c.
26 n.c.
25 n.c.
002aag234
Fig 2. Pin configuration for LQFP48
6.2 Pin description
Table 2.
Symbol
A0
A1
A2
A3
A4
A5
A6
A7
D0
D1
D2
D3
D4
D5
D6
D7
Pin description
Pin Type
3I
4I
5I
6I
9I
10 I
11 I
12 I
37 I/O
38 I/O
41 I/O
42 I/O
45 I/O
46 I/O
1 I/O
2 I/O
Description
Address inputs: selects the bus controller’s internal registers and
ports for read/write operations. Address is registered when CE is
LOW and whether WR or RD transitions LOW. A0 is the least
significant bit.
Data bus: bidirectional 3-state data bus used to transfer
commands, data and status between the bus controller and the
host. D0 is the least significant bit. Data is registered on the rising
edge of WR when CE is LOW.
PCU9661
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 September 2011
© NXP B.V. 2011. All rights reserved.
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PCU9661 전자부품, 판매, 대치품
NXP Semiconductors
PCU9661
Parallel bus to 1 channel UFm I2C-bus controller
7.3.1 Buffer management assumptions
Repeated STARTs will be sent between two consecutive transactions.
After the last operation on a channel is completed, a STOP will be sent.
7.3.2 Buffer size
The PCU9661 serial channel has a 4352-byte buffer assigned to it. The contents of the
buffers should only be modified during channel idle states.
The buffer size represents the memory allocated for the data block only. The slave
address table and configuration bytes are contained in other locations and do not need to
be included in the required buffer size calculation.
For example, to calculate the size of the memory needed to write 26 bytes to 10 slaves:
10 slaves 26 bytes/slave = 260 bytes for the write transactions
A total of 260 bytes of buffer space is required to complete the sequence.
Remark: Note that the bytes required to store the 10 slave addresses are not included in
the calculation since they are stored in the SLATABLE register.
7.4 Error reporting and handling
In case of any transaction error conditions, the device will load the transaction error status
in the STATUS2_[n], generate an interrupt, if unmasked, by pulling down the INT pin and
update the CHSTATUS and CTRLSTATUS registers. The status for the individual SLA
addresses will be stored in the STATUS2_[n] registers.
7.5 Registers
The PCU9661 contains several registers that are used to configure the operation of the
device, status reporting, and to send data. The device also contains global registers for
chip level control and status reporting.
The STATUS2_[n] registers are channel-level direct access registers. The DATA,
SLATABLE, TRANCONFIG, and BYTECOUNT registers are auto-increment registers.
The memory access pointer to the DATA registers can be programmed using the
TRANSEL and TRANOFS registers. See Section 7.5.1.2 “CONTROL — Control register”,
for information on the pointer reset bits BPTRRST and AIPTRRST.
PCU9661
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 September 2011
© NXP B.V. 2011. All rights reserved.
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