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PDF PCU9669 Data sheet ( Hoja de datos )
| Número de pieza | PCU9669 | |
| Descripción | Parallel bus to 1 channel Fm+ and 2 channel UFm I2C-bus controller | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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PCU9669
Parallel bus to 1 channel Fm+ and 2 channel UFm I2C-bus
controller
Rev. 2 — 1 July 2011
Product data sheet
1. General description
The PCU9669 is an advanced single master mode I2C-bus controller. It is a fourth
generation bus controller designed for data intensive I2C-bus data transfers. It has three
independent I2C-bus channels, one of them with data rates up to 1 Mbits/s using the
Fast-mode Plus (Fm+) open-drain topology and two with a much larger transmit only
transfer rate of up to 5 Mbits/s using the new Ultra Fast-mode (UFm) bus with push-pull
topology. Each channel has a generous 4352 byte data buffer which makes the PCU9669
the ideal companion to any CPU that needs to transmit and receive large amounts of
serial data with minimal interruptions.
The PCU9669 is a 8-bit parallel-bus to I2C-bus protocol converter. It can be configured to
communicate with up to 64 slaves in one serial sequence with no intervention from the
CPU. The controller also has a sequence loop control feature that allows it to
automatically retransmit a stored sequence.
Its onboard oscillator and PLL allow the controller to generate the clocks for the I2C-bus
and for the interval timer used in sequence looping. This feature greatly reduces CPU
overhead when data refresh is required in fault tolerant applications.
An external trigger input allows data synchronization with external events. The trigger
signal controls the rate at which a stored sequence is re-transmitted over the I2C-bus.
Error reporting is handled at the transaction level, channel level, and controller level.
A simple interrupt tree and interrupt masks allow further customization of interrupt
management.
The controller parallel bus interface runs at 3.3 V and the I2C-bus I/Os logic levels are
referenced to a dedicated VDD(IO) input pin with a range of 3.0 V to 5.5 V.
2. Features and benefits
Parallel-bus to I2C-bus protocol converter and interface
5 Mbit/s unidirectional data transfer on Ultra Fast-mode (UFm) channel (push-pull
driver)
1 Mbit/s and up to 30 mA SCL/SDA IOL Fast-mode Plus (Fm+) capability
Internal oscillator trimmed to 1 % accuracy reduces external components
Individual 4352-byte buffers for the Fm+ and UFm channels for a total of 13056 bytes
of buffer space
Three levels of reset: individual software channel reset, global software reset, global
hardware RESET pin
Communicates with up to 64 slaves in one serial sequence
1 page  
NXP Semiconductors
PCU9669
Parallel bus to 1 channel Fm+ and 2 channel UFm I2C-bus controller
PCU9669
Product data sheet
Table 2.
Symbol
TRST
TMS
TCK
TDI
TDO
INT
USDA2
USCL2
USDA1
USCL1
SDA0
SCL0
WR
RD
CE
TRIG
RESET
VDD(IO)
VSS(IO)
VDD
VSS
Pin description …continued
Pin Type Description
13 I JTAG test reset input. For normal operation, hold LOW (VSS).
14 I JTAG test mode select input. For normal operation, hold HIGH
(VDD).
15 I JTAG test clock input. For normal operation, hold HIGH (VDD).
16 I JTAG test data in input. For normal operation, hold HIGH (VDD).
17 O JTAG test data out output. For normal operation, do not connect
(n.c.).
20 O Interrupt request: Active LOW, open-drain, output. This pin
requires a pull-up device.
21 O Channel 2 Ultra Fast-mode I2C-bus serial data output.
Push-pull drive. No pull-up device is needed.
22 O Channel 2 Ultra Fast-mode I2C-bus serial clock output.
Push-pull drive. No pull-up device is needed.
25 O Channel 1 Ultra Fast-mode I2C-bus serial data output.
Push-pull drive. No pull-up device is needed.
26 O Channel 1 Ultra Fast-mode I2C-bus serial clock output.
Push-pull drive. No pull-up device is needed.
27 I/O Channel 0 I2C-bus serial data input/output (open-drain).
This pin requires a pull-up device.
28 I/O Channel 0 I2C-bus serial clock input/output (open-drain).
This pin requires a pull-up device.
31 I Write strobe: When LOW and CE is also LOW, the content of the
data bus is loaded into the addressed register. Data are latched on
the rising edge of WR. CE may remain LOW or transition with WR.
32 I Read strobe: When LOW and CE is also LOW, causes the
contents of the addressed register to be presented on the data
bus. The read cycle begins on the falling edge of RD. Data lines
are driven when RD and CE are LOW. CE may transition with RD.
33 I Chip Enable: Active LOW input signal. When LOW, data transfers
between the host and the bus controller are enabled on D0 to D7
as controlled by the WR, RD and A0 to A7 inputs. When HIGH,
places the D0 to D7 lines in the 3-state condition.
During the initialization period, CE must transition with RD until
controller is ready.
34 I Trigger input: provides the trigger to start a new frame.
36 I Reset: Active LOW input. A LOW level resets the device to the
power-on state. Internally pulled HIGH through weak pull-up
current.
24 power I/O power supply: 3.0 V to 5.5 V. Power supply reference for
I2C-bus pins. Sets the voltage reference point for VIL/VIH and the
output drive rail for the UFm channel.
23 power
7, 18, 30, power
40, 44, 48
I/O supply ground. Can be tied to VSS.
Power supply: 3.0 V to 3.6 V. All VDD pins should be connected
together externally.
8, 19, 29, power Supply ground. All VSS pins should be connected together
35, 39,
externally.
43, 47
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 1 July 2011
© NXP B.V. 2011. All rights reserved.
5 of 69
5 Page 
Table 3.
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PCU9669 register address map - direct register access …continued
7 6 5 4 3 2 1 0 Register name Access Write access Description
while
CH active
Default
Size
(bytes)
Channel 2 (UFm) registers
1 1 1 0 0 0 0 0 CONTROL
R/W
yes[1]
channel 2 control ([7] = 1)
00h 1
0 0 0 1 CHSTATUS R
no
channel 2 status ([5:1] = 0 in UFm)
00h 1
0 0 1 0 INTMSK
R/W yes
channel 2 interrupt mask ([5:1] = don’t care) 00h
1
0 0 1 1 SLATABLE
R/W
no
channel 2 slave address table (auto-increment) 00h
64
0 1 0 0 TRANCONFIG R/W
yes, for
channel 2 transaction configuration
TRANCOUNT[2] (auto-increment)
00h 65
0 1 0 1 DATA
R/W yes
channel 2 data (auto-increment)
00h bufsize[3]
0 1 1 0 TRANSEL R/W yes
channel 2 transaction data buffer select
00h
1
0 1 1 1 TRANOFS R/W yes
channel 2 transaction data buffer byte offset 00h
1
1 0 0 0 BYTECOUNT R
no
channel 2 transmitted byte count
(auto-increment)
00h 64
1 0 0 1 FRAMECNT R/W
no
channel 2 frame count
01h 1
1 0 1 0 REFRATE R/W no
channel 2 frame refresh rate
00h 1
1 0 1 1 SCLPER
R/W no
channel 2 clock period
20h 1
1 1 0 0 SDADLY
R/W no
channel 2 SDA delay
08h 1
1 1 0 1 MODE[4]
R/W no
channel 2 mode
83h 1
1 1 1 0-
- no
reserved
00h 1
1 1 1 1 PRESET
R/W yes
channel 2 parallel reset
00h 1
11 Page | ||
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| PDF Descargar | [ Datasheet PCU9669.PDF ] | |
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