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PCU9669 데이터시트 PDF




NXP Semiconductors에서 제조한 전자 부품 PCU9669은 전자 산업 및 응용 분야에서
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부품번호 PCU9669 기능
기능 Parallel bus to 1 channel Fm+ and 2 channel UFm I2C-bus controller
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PCU9669 데이터시트, 핀배열, 회로
PCU9669
Parallel bus to 1 channel Fm+ and 2 channel UFm I2C-bus
controller
Rev. 2 — 1 July 2011
Product data sheet
1. General description
The PCU9669 is an advanced single master mode I2C-bus controller. It is a fourth
generation bus controller designed for data intensive I2C-bus data transfers. It has three
independent I2C-bus channels, one of them with data rates up to 1 Mbits/s using the
Fast-mode Plus (Fm+) open-drain topology and two with a much larger transmit only
transfer rate of up to 5 Mbits/s using the new Ultra Fast-mode (UFm) bus with push-pull
topology. Each channel has a generous 4352 byte data buffer which makes the PCU9669
the ideal companion to any CPU that needs to transmit and receive large amounts of
serial data with minimal interruptions.
The PCU9669 is a 8-bit parallel-bus to I2C-bus protocol converter. It can be configured to
communicate with up to 64 slaves in one serial sequence with no intervention from the
CPU. The controller also has a sequence loop control feature that allows it to
automatically retransmit a stored sequence.
Its onboard oscillator and PLL allow the controller to generate the clocks for the I2C-bus
and for the interval timer used in sequence looping. This feature greatly reduces CPU
overhead when data refresh is required in fault tolerant applications.
An external trigger input allows data synchronization with external events. The trigger
signal controls the rate at which a stored sequence is re-transmitted over the I2C-bus.
Error reporting is handled at the transaction level, channel level, and controller level.
A simple interrupt tree and interrupt masks allow further customization of interrupt
management.
The controller parallel bus interface runs at 3.3 V and the I2C-bus I/Os logic levels are
referenced to a dedicated VDD(IO) input pin with a range of 3.0 V to 5.5 V.
2. Features and benefits
Parallel-bus to I2C-bus protocol converter and interface
5 Mbit/s unidirectional data transfer on Ultra Fast-mode (UFm) channel (push-pull
driver)
1 Mbit/s and up to 30 mA SCL/SDA IOL Fast-mode Plus (Fm+) capability
Internal oscillator trimmed to 1 % accuracy reduces external components
Individual 4352-byte buffers for the Fm+ and UFm channels for a total of 13056 bytes
of buffer space
Three levels of reset: individual software channel reset, global software reset, global
hardware RESET pin
Communicates with up to 64 slaves in one serial sequence




PCU9669 pdf, 반도체, 판매, 대치품
NXP Semiconductors
PCU9669
Parallel bus to 1 channel Fm+ and 2 channel UFm I2C-bus controller
6. Pinning information
6.1 Pinning
D6 1
D7 2
A0 3
A1 4
A2 5
A3 6
VDD
VSS
A4
7
8
9
A5 10
A6 11
A7 12
PCU9669B
36 RESET
35 VSS
34 TRIG
33 CE
32 RD
31 WR
30 VDD
29 VSS
28 SCL0
27 SDA0
26 USCL1
25 USDA1
002aaf480
Fig 2. Pin configuration for LQFP48
6.2 Pin description
Table 2.
Symbol
A0
A1
A2
A3
A4
A5
A6
A7
D0
D1
D2
D3
D4
D5
D6
D7
Pin description
Pin Type
3I
4I
5I
6I
9I
10 I
11 I
12 I
37 I/O
38 I/O
41 I/O
42 I/O
45 I/O
46 I/O
1 I/O
2 I/O
Description
Address inputs: selects the bus controller’s internal registers and
ports for read/write operations. Address is registered when CE is
LOW and whether WR or RD transitions LOW. A0 is the least
significant bit.
Data bus: bidirectional 3-state data bus used to transfer
commands, data and status between the bus controller and the
host. D0 is the least significant bit. Data is registered on the rising
edge of WR when CE is LOW.
PCU9669
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 1 July 2011
© NXP B.V. 2011. All rights reserved.
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PCU9669 전자부품, 판매, 대치품
NXP Semiconductors
PCU9669
Parallel bus to 1 channel Fm+ and 2 channel UFm I2C-bus controller
After sending all the commands and data it wanted to the I2C-bus controller, the host
could either continue to program data for other channels or write to the CONTROL
register to begin data transmission on the current channel. The transactions will be sent
on the I2C-bus in the order in which the slave addresses are listed in the SLATABLE,
separated by a RESTART condition. The last transaction in the sequence will end with a
STOP condition.
If during a READ command a NACK on the slave address is received, the buffer space
allocated for the read will remain untouched and will contain the last information written in
that location. A buffer read on the parallel bus should only be done after a valid buffer
state is reached to guarantee data valid (see Section 7.5.1.1 “STATUS0_[n],
STATUS1_[n], STATUS2_[n] — Transaction status registers”).
To program data for another channel, that channel is selected and data programmed as
described above. One or more channels can be busy with serial transmission while
additional parallel-bus data is sent to the buffer of an idle channel.
7.3.1 Buffer management assumptions
Repeated STARTs will be sent between two consecutive transactions.
After the last operation on a channel is completed, a STOP will be sent.
In a READ transaction, after the last data byte has been received from a particular
slave, a NACK is sent to the slave.
7.3.2 Buffer sizes
The PCU9669 channels have individual buffers assigned to them. The contents of the
buffers should only be modified during channel idle states.
The memory allocation is 4352 bytes per channel.
The buffer sizes represent the memory allocated for the data block only. The slave
address table and configuration bytes are contained in other locations and do not need to
be included in the required buffer size calculation.
For example, to calculate the size of the memory needed to write 26 bytes to 10 slaves
and to read 2 bytes from 4 slaves (no command bytes required for the read):
10 slaves 26 bytes/slave = 260 bytes for the write transactions
4 slaves 2 bytes/slave = 8 bytes for the read transactions
A total of 268 bytes of buffer space is required to complete the sequence.
Remark: Note that the bytes required to store the 30 slave addresses are not included in
the calculation since they are stored in the SLATABLE register.
PCU9669
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 1 July 2011
© NXP B.V. 2011. All rights reserved.
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