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PDF ML610Q359 Data sheet ( Hoja de datos )
| Número de pieza | ML610Q359 | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | LAPIS Semiconductor | |
| Logotipo |  |
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ML610Q359/ML610Q360
8-bit Microcontroller with Voice Output Function
FEDL610Q359-01
Issue Date: Jul 31, 2015
GENERAL DESCRIPTION
Equipped with a 8-bit CPU nX-U8/100, the ML610Q359 is a high-performance 8-bit CMOS microcontroller that integrates a
wide variety of peripherals such as, 12-bit A/D converter, timer, synchronous serial port, UART, and voice output function.
The nX-U8/100 CPU is capable of executing instructions efficiently on a one-instruction-per-clock-pulse basis through parallel
processing by the 3-stage pipelined architecture.
In addition, it has an on-chip debugging function, which allows software debugging/rewriting with the LSI mounted on the
board.
FEATURES
• CPU
− 8-bit RISC CPU (CPU name: nX-U8/100)
− Instruction system: 16-bit instructions
− Instruction set:Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,
bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
− On-Chip debug function
− Minimum instruction execution time
Approx 30.5 µs (at 32.768kHz system clock)
Approx 0.125 µs (at 8MHz system clock)＠DVDD = 2.2 to 3.6V
Approx 0.250 µs (at 4MHz system clock)＠DVDD = 2.0 to 3.6V
• Internal memory
− Has 160-Kbyte flash ROM(80K × 16-bit) built in. (544 byte of test domain that it cannot be used is included)
− Has 3-Kbyte flash ROM built in. (area in which self rewriting is possible.512Byte×6)
− Has 2-Kbyte RAM (2048 × 8 bits) built in.
− Has 16-Mbit P2ROM built in. (only ML610Q360)
• Interrupt controller
− 2 non-maskable interrupt sources (Internal source: 1, External source: 1)
− 25 maskable interrupt sources (Internal source: 19, External source: 6)
• Time base counter
− Low-speed time base counter × 1 channel
− High-speed time base counter × 1 channel
• Watchdog timer
− Generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)
• Timers
− 8 bits × 8ch (16-bit configuration available)
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1 page  
Block Diagram of ML610Q360
FEDL610Q359-01
ML610Q359/ML610Q360
EPSW1～3
PSW
Timing
Controller
On-Chip
ICE
CPU (nX-U8/100)
GREG
0～15
ELR1～3
LR
EA
ALU
SP
Instruction
Decoder
Instruction
Register
ECSR1～3
DSR/CSR
PC
BUS
Controller
Program
Memory
（Flash）
160Kbyte
DVDD
DVSS
Data-bus
RESET_N
TEST0
TEST1_N
XT0
XT1
LSCLK*
OUTCLK*
VDDL
VDDX
AVDD
AVSS
AIN0 to AIN２
AVDD
AVSS
VDDR
RESET &
TEST
OSC
POWER
12bit-ADC
INT
1
VDDR
RAM
2048byte
Interrupt
Controller
INT
4
TBC
INT
8 8bit Timer
×8
INT
WDT
Temperature
sensor
DVDD
DVSS
SVS
*1 PVPP
*1 16Mbit
P2ROM
PSO
PSCK
PSI
PCSB
* *1 P54(SIN1)
* *1 P55(SCK1)
* *1 P56(SOUT1)
*1 P57
PORT
INT
2
SSIO
SCK0*
SIN0*
SOUT0*
INT
3
UART
INT
7
GPIO
INT
1
VOICECNT
SPEAKER
AMP
RXD0*,
RXD1*
RXD2*
TXD0*
TXD1*
TXD2*
NMI
P00 to P05
P10
P20 to P22
P30 to P37
P40 to P47
P50 to P53 *１
TESTO3
to TESTO6 *1
P60 to P63
SG
AOUT
SPVDD
SPVSS
SG
SPIN
SPP
SPM
* : Secondary or tertiary or fourthly function
*1: It is the point with the difference in ML610Q359 and ML610Q360
Figure 2 Block Diagram of ML610Q360
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5 Page 
FEDL610Q359-01
ML610Q359/ML610Q360
Complement: It is only ML610Q360. ML610Q359 does not correspond.
P54-P57 are connected with built-in P2ROM inside the chip, and each function exists. An external terminator name is set to
TESTO3-TESTO6. Please make the external terminator open. The content of contact with P2ROM is shown below.
The terminator of built-in P2ROM
PSO
PSCK
PSI
PCSB
Explanation
serial data output
It connects with P54/SIN1(tertiary functional use) inside.
serial clock input
It connects with P55/SCK1(tertiary functional use) inside.
serial data input
It connects with P56/SOUT1(tertiary functional use) inside.
chip select input
It connects with P57(primary functional use) inside.
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ML610Q359.PDF ] | |
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