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PDF ML620Q152A Data sheet ( Hoja de datos )
| Número de pieza | ML620Q152A | |
| Descripción | 16-bit micro controller | |
| Fabricantes | LAPIS Semiconductor | |
| Logotipo |  |
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FEDL620Q150A-01
Issue Date: May 7, 2015
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
16-bit micro controller
GENERAL DESCRIPTION
This LSI is a high-performance 16-bit CMOS microcontroller into which rich peripheral circuits, such as 10-bit A/D converter,
timer, PWM, synchronous serial port, UART, I2C bus interface (master), Low level detect circuit, are incorporated around 16-bit
CPU nX-U16/100.
The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by 3-stage pipe line architecture
parallel procesing. and, this LSI has a data flash-memory fill area by a software which can be written in. In addition, it has an
on-chip debugging function, which allows software debugging/rewriting with the LSI mounted on the board.
FEATURES
• CPU
− 16-bit RISC CPU (CPU name: nX-U16/100)
− Instruction system:16-bit instructions
− Instruction set:Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,
bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
− On-Chip debug function
− Minimum instruction execution time
Approx 30.5 µs (at 32.768kHz system clock)
Approx 0.122 µs (at 8.192MHz system clock)
• Internal memory
− Flash-memory
Product
Program area
ML620Q151A/ML620Q154A/ML620Q157A
32-Kbyte* (16K × 16-bit)
ML620Q152A/ML620Q155A/ML620Q158A
48-Kbyte* (24K × 16-bit)
ML620Q153A/ML620Q156A/ML620Q159A
64-Kbyte* (32K × 16-bit)
* including unusable 1KByte TEST area
Internal 2-Kbyte Data Flash (1-Kbyte × 2) Rewrite cycle: 10,000 times
− SRAM: Internal 2-Kbyte RAM (2-Kbyte × 8 -bits)
Rewrite
cycle
100
• Interrupt controller
− 2 non-maskable interrupt sources (Internal source: BACK-UP CLOCK, WDT)
− maskable interrupt
Product
Interrupt source
ML620Q151A/ML620Q154A/ML620Q157A
27 (Internal source: 20, External source: 7)
ML620Q152A/ML620Q155A/ML620Q158A
28 (Internal source: 20, External source: 8)
ML620Q153A/ML620Q156A/ML620Q159A
28 (Internal source: 20, External source: 8)
− 4 steps of interrupt level, and a mask function
1/36
1 page  
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
BLOCK DIAGRAM
Block Diagram of ML620Q151A/ML620Q152A/ML620Q153A(TQFP48)
EPSW1 3
PSW
Timing
Controller
On-Chip
ICE
CPU (nX-U16/100)
GREG
0 15
ELR1 3
LR
EA
ALU
SP
Instruction
Decoder
Instruction
Register
ECSR1 3
DSR/CSR
PC
BUS
Controller
Program
Memory
(FLASH)
32/48/64Kbyte
VDD
VSS
VDDL
Power
RESET N
TEST0*3
TEST1_N
XT0
XT1
LSCLK*
OUTCLK*
RESET &
TEST
OSC
INT
1
VDD
VREF
AIN0 to AIN11
CMP0P
CMP0M
SA-ADC
INT
1
Analog
Comparator
×1
INT
1
Data-bus
RAM
2Kbyte
Interrupt
Controller
INT
1 WDT
INT
4 TBC
INT
1
LLD
INT
1 SSIOx1
INT
2
UARTx1
(*1)
INT
1 I2Cx1
INT
6 8bit Timer
×2
16bit Timer
×4
INT
4 16bitTimer
with PWMx4
INT
7
GPIO
* Secondary or tertiary or quaternary function
*1 Full-duplex × 1ch ( Half-duplex × 2ch )
*2 Cannot be used as I/O port when connecting the crystal resonator
*3 Cannot be used as I/O port when connecting the uEASE(On-chip debug emualtor)
SCK0*
SIN0*
SOUT0*
RXD0*
TXD0*
RXD1*
TXD1*
SDA0*
SCL0*
TMHAOUT*
TMHBOUT*
PWM4*
PWM5*
PWM6*
PWM7*
PW45EV0*
PW45EV1*
PW67EV0*
PW67EV1*
P00 to P04
P12*2
P13*2
P14*3
P20 to P23
P30 to P35
P40 to P47
P54 to P57
P60 to P63
P80 to P87
Figure 1-1 Block Diagram of ML620Q151A/ML620Q152A/ML620Q153A(TQFP48)
5/36
5 Page 
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
List of Pins
48 52 64
Pin Pin Pin
No. No. No.
333
555
444
46 50 62
47 51 63
48 52 64
111
222
666
37 40 49
38 41 50
39 42 51
40 43 52
41 44 53
⎯ 45 54
Primary function
Pin
name
I/O
Description
Vss
VDD
VDDL
P14/
TEST0
⎯
Negative power
supply pin
⎯
Positive power
supply pin
Power supply for
⎯ internal logic
(internally generated)
I
Input port/
Input pin for testing
RESET_N I Reset input pin
TEST1_N I Input pin for testing
P12/
XT0
Input port/
I Low-speed clock
oscillation pin
P13/
XT1
Input/output port/
I/O Low-speed clock
oscillation pin
Reference power
VREF
⎯
supply pin of
Successive-approxi
mation type ADC
P00/EXI0/
PW45EV0
I
Input port /
External interrupt /
PW45EV0 input
P01/EXI1/
PW67EV0
I
Input port /
External interrupt /
PW67EV0 input
P02/EXI2/
RXD0
Input port /
I External interrupt
UART0 data input
P03/EXI3/
RXD1
Input port /
I External interrupt
UART1 data input
P04/EXI4
I
Input port /
External interrupt
P05/EXI5
I
Input port /
External interrupt
42 46 55
P20/
LED0/
O
Output port / LED
drive
43 47 56
P21/
LED1/
O
Output port / LED
drive
44 48 57
P22/
LED2/
O
Output port / LED
drive
45 49 58
P23/
LED3/
O
Output port / LED
drive
Input/output port /
P30/EXI6
PW45EV1 input /
7 7 7 PW45EV1/ I/O Successive
AIN0
approximation type
ADC input
Input/output port /
P31/EXI7
PW67EV1 input /
8 8 8 PW67EV1/ I/O Successive
AIN1
approximation type
ADC input
Input/output port /
P32/
PW45EV0 input /
9 9 9 PW45EV0/ I/O Successive
AIN2
approximation type
ADC input
10
10
10
P33/
PW67EV0/
AIN3
I/O
Input/output port /
PW67EV0 input /
Successive
approximation type
Secondary function
Pin
name
I/O
De-
scription
⎯ ⎯⎯
⎯ ⎯⎯
⎯ ⎯⎯
⎯ ⎯⎯
⎯ ⎯⎯
⎯ ⎯⎯
⎯ ⎯⎯
⎯ ⎯⎯
⎯ ⎯⎯
⎯ ⎯⎯
⎯ ⎯⎯
⎯ ⎯⎯
⎯ ⎯⎯
⎯ ⎯⎯
⎯ ⎯⎯
Low-spe
LSCLK O ed clock
output
Low-spe
OUTCLK O ed clock
output
⎯ ⎯⎯
⎯ ⎯⎯
⎯ ⎯⎯
⎯ ⎯⎯
⎯ ⎯⎯
⎯ ⎯⎯
Tertiary function
Pin
name
I/O
De-
scription
⎯⎯⎯
⎯⎯⎯
⎯⎯⎯
⎯⎯⎯
⎯⎯⎯
⎯⎯⎯
⎯⎯⎯
⎯⎯⎯
⎯⎯⎯
⎯⎯⎯
⎯⎯⎯
⎯⎯⎯
⎯⎯⎯
⎯⎯⎯
⎯⎯⎯
PWM4
O
PWM4
output
PWM5
O
PWM5
output
TMHAO
UT
O
TimerA
output
TMHBO
UT
O
TimerB
output
⎯⎯⎯
⎯⎯⎯
⎯⎯⎯
⎯⎯⎯
Quaternary function
Pin
name
I/O
De-
scription
⎯⎯
⎯
⎯⎯
⎯
⎯⎯
⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯
⎯
⎯
⎯
⎯⎯
⎯
⎯⎯
⎯
⎯⎯
⎯
⎯⎯
⎯⎯
⎯
⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯
⎯
⎯
⎯
⎯⎯
PWM6 O
PWM7 O
⎯
PWM6
output
PWM7
output
⎯⎯
⎯
⎯⎯
⎯
⎯⎯
⎯
⎯⎯
⎯
11/36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ML620Q152A.PDF ] | |
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