PDF ML630Q791 Data sheet ( Hoja de datos )

Número de pieza	ML630Q791
Descripción	32-bit Microcontroller
Fabricantes	LAPIS Semiconductor
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No Preview Available ! ML630Q791 32-bit Microcontroller for Sensor Control FEDL630Q791-01 Issue Date: 10/22/2014 GENERAL DESCRIPTION The ML630Q791 is a high-performance low power 32-bit microcontroller optimized for the control of various sensor ICs. Equipped with a 32-bit CPU core Cortex®-M0, it implements a 128 KB flash memory, 16 KB RAM, rich interfaces used to control various sensors, and host interface with the 512-byte communication register in a very compact package. The ML630Q791 can efficiently control the power consumption of the whole system by separating the sensor control function from the application processor, and its high performance permits sensor-fusion using accelerometers, magnetic field sensors and gyro sensors, which makes it an ideal sensor control microcontroller for smart phones. FEATURES ● CPU — 32-bit RISC CPU (ARM® Cortex®-M0) — Thumb®/Thumb®-2 instruction supported — Serial Wire Debug (SWD) port support ● Internal memory — 128 KB FLASH ROM (32K x 32-bit) — 16 KB SRAM (4K x 32-bit) ● Interrupt controller — Non-maskable interrupt: 1 source — Maskable interrupt: 21 sources Internal sources: 14 (Timer: 8, PWM: 1, I2C: 2, HOSTIF: 1, Arithmetic circuit: 1, UART: 1) External sources: 7 ● Timer / Counter — 8-bit auto-reload timer x 8channels — 16-bit pulse width modulation(PWM) x 1channel — Watchdog timer (WDT) x 1channel ● Serial interface — I2C interface with master function x 2channels (including 8-bit, 32-stage FIFO) — UART interface x 1channel (two-wire, full duplex communication, including 8-bit, 32-stage FIFO) ● Host interface — Serial interface with slave function (SPI/I2C selectable) x 1channel — Interrupt to a host processor — 512Byte FIFO RAM ● General-purpose I/O port — 7-bit input/output port x 1channel — External Interrupt function ● Arithmetic circuit — Root and Division operations support ● Flash Programming Function — Hardware remap function support — ISP(In System Programming) support ARM, Cortex and Thumb are registered trademarks of ARM Limited 1/25 1 page FEDL630Q791-01 ML630Q791 PIN FUNCTION Pin List PIN Primary Function Secondary Function No. Symbol I/O Reset Function State Symbol I/O Function D3 GND — D1 VDD — D2 VDDL — A2 CLK I B4 BRMP I A3 SWC I B3 SWD IO C1 RESET_N I A1 SCL_S1 I SCLK_S I B2 SDA_S1 IO SDIO_S IO SDI_S I D5 PA4 IO C5 PA5 IO B5 SDA0_M IO A5 SCL0_M O C4 PA2 IO D4 PA3 IO C3 PA0 IO C2 PA1 IO B1 PA6 IO A4 VPP — — Power Supply — Power Supply — Power Supply HZ SYSTEM PD SYSTEM PU DEBUG I/F PU DEBUG I/F PU SYSTEM HZ HSTIF — — — — — — — — — — — — — — — — — — HZ HSTIF —— HZ GPIO SCS_S I HZ GPIO SDO_S O HZ I2C0 —— HZ I2C0 HZ GPIO — RXD0 — I HZ GPIO TXD0 O HZ GPIO SDA1_M IO HZ GPIO SCL1_M O HZ GPIO INT0_S O — TEST —— — — — — — — — — — — HSTIF HSTIF — — UART UART I2C1 I2C1 HSTIF — *1 The used pin is determined by the HSTIF setting. Tertiary Function Symbol I/O Function ——— ——— ——— ——— ——— ——— ——— ——— ——— — — — — — — — PWM0 INT1_S — — — — — — — — — IO O — — — — — — — — — PWM HSTIF — — 5/25 5 Page FEDL630Q791-01 ML630Q791 Configuration Register CFG CFG 7 REGMD 6 — R/W Initial Value R/W 0 — 0 54 INTPW[1:0] R/W R/W 00 3 INT1EN R/W 0 2 INTLVL R/W 0 1 — — 0 0 — — 0 REGMD: This bit shows the register access mode of the serial interface (SPI/I2C). When set to "0", the internal address is incremented by 1 each time a 1-byte data is transmitted/received. When set to "1", the address is fixed to the same address. INTPW[1:0]: This bit indicates the pulse width setting when the interrupt signal is a pulse signal. If the pulse width is set to 500[ns] or longer, an interrupt pulse may not be output depending on the timing when the CPU writes to the interrupt request register. In this case, use the level output as the interrupt signal instead of the pulse output. INTPW[1:0] 00 01 10 11 Description 250[ns] (4 MHz cycle) (initial value) 500[ns] (2 MHz cycle) 1000[ns] (1 MHz cycle) 2000[ns] (500 kHz cycle) INT1EN: Controls the INT1_S interrupt signal. INT1EN 0 1 Description INT1_S pin is merged with INT0_S to be output (initial value) INT1_S pin is enabled INTLVL: Sets the interrupt level. Set to "0" for pulse output, or set to "1" for level output. 11/25 11 Page

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