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부품번호 NX3L4053 기능
기능 Triple low-ohmic single-pole double-throw analog switch
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NX3L4053 데이터시트, 핀배열, 회로
NX3L4053
Triple low-ohmic single-pole double-throw analog switch
Rev. 5 — 25 June 2012
Product data sheet
1. General description
The NX3L4053 is a triple low-ohmic single-pole double-throw analog switch, suitable for
use as an analog or digital multiplexer/demultiplexer. Each switch has a digital select input
(nS), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). All
three switches share an enable input (E). A digital enable pin E is common to all
switches.When E is HIGH, the switches are turned off.
Schmitt trigger action at the digital inputs makes the circuit tolerant to slower input rise and
fall times. Low threshold digital inputs allows this device to be driven by 1.8 V logic levels
in 3.3 V applications without significant increase in supply current ICC. This makes it
possible for the NX3L4053 to switch 4.3 V signals with a 1.8 V digital controller,
eliminating the need for logic level translation. The NX3L4053 allows signals with
amplitude up to VCC to be transmitted from nZ to nY0 or nY1; or from nY0 or nY1 to nZ. Its
low ON resistance (0.5 ) and flatness (0.13 ) ensures minimal attenuation and
distortion of transmitted signals.
2. Features and benefits
Wide supply voltage range from 1.4 V to 4.3 V
Very low ON resistance (peak):
1.8 (typical) at VCC = 1.4 V
1.0 (typical) at VCC = 1.65 V
0.6 (typical) at VCC = 2.3 V
0.6 (typical) at VCC = 2.7 V
0.5 (typical) at VCC = 4.3 V
Break-before-make switching
High noise immunity
ESD protection:
HBM JESD22-A114F Class 3A exceeds 4000 V
MM JESD22-A115-A exceeds 200 V
CDM AEC-Q100-011 revision B exceeds 1000 V
IEC61000-4-2 contact discharge exceeds 6000 V for switch ports
CMOS low-power consumption
Latch-up performance exceeds 100 mA per JESD 78 Class II Level A
1.8 V control logic at VCC = 3.6 V
Control input accepts voltages above supply voltage
Very low supply current, even when input is below VCC
High current handling capability (350 mA continuous current under 3.3 V supply)
Specified from 40 C to +85 C and from 40 C to +125 C




NX3L4053 pdf, 반도체, 판매, 대치품
NXP Semiconductors
NX3L4053
Triple low-ohmic single-pole double-throw analog switch
7.2 Pin description
Table 3. Pin description
Symbol
Pin
SOT1039-2
E4
n.c. 5
GND
6
1S, 2S, 3S
9, 8, 7
1Y0, 2Y0, 3Y0
10, 16, 3
1Y1, 2Y1, 3Y1
11, 15, 1
1Z , 2Z, 3Z
12, 13, 2
VCC 14
8. Functional description
SOT403-1
6
7
8
11, 10 ,9
12, 2, 5
13, 1, 3
14, 15, 4
16
Description
enable input (active LOW)
not connected
ground (0 V)
select input
independent input or output
independent input or output
independent output or input
supply voltage
Table 4.
Inputs
E
L
L
H
Function table
nS
L
H
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
9. Limiting values
Channel on
nY0 to nZ
nY1 to nZ
switches off
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC supply voltage
VI input voltage
nS and E
VSW switch voltage
IIK input clamping current VI < 0.5 V
ISK switch clamping current VI < 0.5 V or VI > VCC + 0.5 V
ISW switch current
VSW > 0.5 V or VSW < VCC + 0.5 V;
source or sink current
0.5
[1] 0.5
[2] 0.5
50
-
-
+4.6
V
+4.6
V
VCC + 0.5 V
- mA
50 mA
350
mA
VSW > 0.5 V or VSW < VCC + 0.5 V;
pulsed at 1 ms duration, < 10 % duty cycle;
peak current
-
500
mA
Tstg storage temperature
Ptot total power dissipation Tamb = 40 C to +125 C
HXQFN16
65
[3] -
+150
250
C
mW
TSSOP16
[4] -
500 mW
[1] The minimum input voltage rating may be exceeded if the input current rating is observed.
NX3L4053
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
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NX3L4053 전자부품, 판매, 대치품
NXP Semiconductors
NX3L4053
Triple low-ohmic single-pole double-throw analog switch
VIL or VIH
VIL
VCC
nS
nZ
IS
E
VI
nY0 1
nY1 2
switch
GND
VI = 0.3 V or VCC 0.3 V; VO = VCC 0.3 V or 0.3 V.
Fig 6. Test circuit for measuring ON-state leakage current
switch
1
2
nS
VIL
VIH
E
VIL
VIL
VO
001aal740
11.2 ON resistance
Table 8. ON resistance[1]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 8 to Figure 14.
Symbol Parameter
Conditions
Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Min Typ[2] Max
Min
Max
RON(peak) ON resistance
(peak)
RON
ON resistance
mismatch
between
channels
RON(flat) ON resistance
(flatness)
VI = GND to VCC;
ISW = 100 mA; see Figure 7
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 4.3 V
VI = GND to VCC;
ISW = 100 mA
[3]
VCC = 1.4 V; VSW = 0.4 V
VCC = 1.65 V; VSW = 0.5 V
VCC = 2.3 V; VSW = 0.7 V
VCC = 2.7 V; VSW = 0.8 V
VCC = 4.3 V; VSW = 0.8 V
VI = GND to VCC;
ISW = 100 mA
[4]
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 4.3 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.8 3.8
1.0 1.7
0.6 0.9
0.6 0.80
0.5 0.80
0.23 0.38
0.23 0.28
0.12 0.15
0.12 0.15
0.12 0.15
1.0 3.3
0.5 1.2
0.15 0.3
0.13 0.3
0.2 0.4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4.2
1.8
1.0
1.0
1.0
0.38
0.38
0.18
0.18
0.18
3.6
1.3
0.35
0.35
0.45
[1] For NX3L4053PW (TSSOP16 package), all ON resistance values are up to 0.05 higher.
[2] Typical values are measured at Tamb = 25 C.
[3] Measured at identical VCC, temperature and input voltage.
[4] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and
temperature.
NX3L4053
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
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