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PDF EFM8BB1 Data sheet ( Hoja de datos )
| Número de pieza | EFM8BB1 | |
| Descripción | microcontrollers | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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EFM8 Busy Bee Family
EFM8BB1 Data Sheet
The EFM8BB1, part of the Busy Bee family of MCUs, is a multi-
purpose line of 8-bit microcontrollers with a comprehensive feature
set in small packages.
These devices offer high-value by integrating advanced analog and communication pe-
ripherals into small packages, making them ideal for space-constrained applications.
With an efficient 8051 core, enhanced pulse-width modulation, and precision analog, the
EFM8BB1 family is also optimal for embedded applications.
EFM8BB1 applications include the following:
• Motor control
• Consumer electronics
• Sensor controllers
• Medical equipment
• Lighting systems
• I/O port expander
KEY FEATURES
• Pipelined 8-bit C8051 core with 25 MHz
maximum operating frequency
• Up to 18 multifunction, 5 V tolerant I/O pins
• One 12-bit Analog to Digital converter
(ADC)
• Two low-current analog comparators
• Integrated temperature sensor
• 3-channel enhanced PWM / PCA
• Four 16-bit timers
• UART, SPI and SMBus/I2C
• Priority crossbar for flexible pin mapping
Core / Memory
CIP-51 8051 Core
(25 MHz)
Clock Management
External CMOS
Oscillator
High Frequency
RC Oscillator
Energy Management
Internal LDO
Regulator
Power-On Reset
Flash Program
Memory
(up to 8 KB)
RAM Memory
(up to 512 bytes)
Debug Interface
with C2
Serial Interfaces
UART
SPI
I2C / SMBus
I/O Ports
External
Interrupts
Pin Reset
General Purpose I/O
Low Frequency
RC Oscillator
8-bit SFR bus
Timers and Triggers
16-bit
Timers
PCA/PWM
Watchdog Timer
Brown-Out Detector
Analog Interfaces
ADC
Analog
Comparators
Internal Voltage Reference
Security
16-bit CRC
Lowest power mode with peripheral operational:
Normal
Idle
Shutdown
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EFM8BB1 Data Sheet
System Overview
3.2 Power
All internal circuitry draws power from the VDD supply pin. External I/O pins are powered from the VIO supply voltage (or VDD on devi-
ces without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over the
device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when
not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little
power when they are not in use.
Table 3.1. Power Modes
Power Mode
Normal
Idle
Shutdown
Details
Core and all peripherals clocked and fully operational
• Core halted
• All peripherals clocked and fully operational
• Code resumes execution on wake event
• All internal power nets shut down
• Pins retain state
• Exit on pin or power-on reset
Mode Entry
—
Set IDLE bit in PCON0
1. Set STOPCF bit in
REG0CN
2. Set STOP bit in
PCON0
Wake-Up Sources
—
Any interrupt
• RSTb pin reset
• Power-on reset
3.3 I/O
Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P1.7 can be defined as gen-
eral-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an
analog function. Port pins P2.0 and P2.1 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P2.0.
• Up to 18 multi-functions I/O pins, supporting digital and analog functions.
• Flexible priority crossbar decoder for digital peripheral assignment.
• Two drive strength settings for each port.
• Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1).
• Up to 16 direct-pin interrupt sources with shared interrupt vector (Port Match).
3.4 Clocking
The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system
clock comes up running from the 24.5 MHz oscillator divided by 8.
• Provides clock to core and peripherals.
• 24.5 MHz internal oscillator (HFOSC0), accurate to ±2% over supply and temperature corners.
• 80 kHz low-frequency oscillator (LFOSC0).
• External CMOS clock input (EXTCLK).
• Clock divider with eight settings for flexible clock scaling: Divide the selected clock source by 1, 2, 4, 8, 16, 32, 64, or 128.
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Parameter
ADC0 Always-on4
Symbol
IADC
ADC0 Burst Mode, 10-bit single
conversions, external reference
IADC
ADC0 Burst Mode, 10-bit single
conversions, internal reference,
Low power bias settings
IADC
ADC0 Burst Mode, 12-bit single
conversions, external reference
IADC
ADC0 Burst Mode, 12-bit single
conversions, internal reference
IADC
Internal ADC0 Reference, Always- IVREFFS
on5
Temperature Sensor
Comparator 0 (CMP0),
Comparator 1 (CMP1)
ITSENSE
ICMP
Voltage Supply Monitor (VMON0) IVMON
Test Condition
800 ksps, 10-bit conversions or
200 ksps, 12-bit conversions
Normal bias settings
VDD = 3.0 V
250 ksps, 10-bit conversions or
62.5 ksps 12-bit conversions
Low power bias settings
VDD = 3.0 V
200 ksps, VDD = 3.0 V
100 ksps, VDD = 3.0 V
10 ksps, VDD = 3.0 V
200 ksps, VDD = 3.0 V
100 ksps, VDD = 3.0 V
10 ksps, VDD = 3.0 V
100 ksps, VDD = 3.0 V
50 ksps, VDD = 3.0 V
10 ksps, VDD = 3.0 V
100 ksps, VDD = 3.0 V,
Normal bias
50 ksps, VDD = 3.0 V,
Low power bias
10 ksps, VDD = 3.0 V,
Low power bias
Normal Power Mode
Low Power Mode
CPMD = 11
CPMD = 10
CPMD = 01
CPMD = 00
EFM8BB1 Data Sheet
Electrical Specifications
Min Typ Max Unit
—
845 1200
µA
— 425 580 µA
— 370 —
— 185 —
— 19 —
— 490 —
— 245 —
— 23 —
— 530 —
— 265 —
— 53 —
— 950 —
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
— 420 —
µA
— 85 — µA
— 680 790 µA
— 160 210 µA
— 75 120 µA
— 0.5 — µA
— 3 — µA
— 10 — µA
— 25 — µA
— 15 20 µA
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Rev. 1.1 | 10
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EFM8BB1.PDF ] | |
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