|
|
PDF EFM8SB2 Data sheet ( Hoja de datos )
| Número de pieza | EFM8SB2 | |
| Descripción | microcontrollers | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de EFM8SB2 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
EFM8 Sleepy Bee Family
EFM8SB2 Data Sheet
The EFM8SB2, part of the Sleepy Bee family of MCUs, is the
world’s most energy friendly 8-bit microcontrollers with a compre-
hensive feature set in small packages.
These devices offer lowest power consumption by combining innovative low energy tech-
niques and short wakeup times from energy saving modes into small packages, making
them well-suited for any battery operated applications. With an efficient 8051 core, 6-bit
current reference, and precision analog, the EFM8SB2 family is also optimal for embed-
ded applications.
EFM8SB2 applications include the following:
• Hand-held devices
• Industrial controls
• Battery-operated consumer electronics
• Sensor interfaces
ENERGY FRIENDLY FEATURES
• Lowest MCU sleep current with supply
brownout detection (50 nA)
• Lowest MCU active current with these
features (170 μA / MHz at 24.5 MHz clock
rate)
• Lowest MCU sleep current using internal
RTC operating and supply brownout
detection (<300 nA)
• Ultra-fast wake up for digital and analog
peripherals (< 2 μs)
• Integrated low drop out (LDO) voltage
regulator to maintain ultra-low active
current at all voltages
Core / Memory
CIP-51 8051 Core
(25 MHz)
Clock Management
External
Oscillator
Low Power 20
MHz RC
Oscillator
Energy Management
Internal LDO
Regulator
Power-On Reset
Flash Program
Memory
(up to 64 KB)
RAM Memory
(4352 bytes)
Debug Interface
with C2
External 32 kHz
RTC Oscillator
High Frequency
24.5 MHz RC
Oscillator
Brown-Out Detector
Serial Interfaces
UART
2 x SPI
I2C / SMBus
I/O Ports
External
Interrupts
Pin Reset
General
Purpose I/O
Pin Wakeup
8-bit SFR bus
Timers and Triggers
Timers
0/1/2/3
PCA/PWM
Watchdog
Timer
Real Time
Clock
Analog Interfaces
ADC
Comparator 0
Comparator 1
Internal Voltage
Reference
Internal Current Reference
Security
16/32-bit CRC
Lowest power mode with peripheral operational:
Normal
Idle
Suspend
Sleep
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.1
1 page  
3. System Overview
3.1 Introduction
EFM8SB2 Data Sheet
System Overview
C2CK/RSTb
VDD
GND
Power On
Reset/PMU
Wake
Reset
Debug /
Programming
Hardware
CIP-51 8051 Controller
Core
64/32/16 KB ISP Flash
Program Memory
256 Byte SRAM
4096 Byte XRAM
C2D
Power Net
Analog
Power
VREG
Digital
Power
SYSCLK
System Clock
Configuration
Precision
24.5 MHz
Oscillator
SFR
Bus
Port I/O Configuration
Digital Peripherals
UART
Timers 0,
1, 2, 3
PCA/WDT
SMBus
SPI 0,1
CRC
Priority
Crossbar
Decoder
Crossbar Control
External Memory Interface
Control
Address
Data
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
XTAL3
XTAL4
XTAL1
XTAL2
Low Power
20 MHz
Oscillator
External
Oscillator
Circuit
RTC
Oscillator
Analog Peripherals
Internal External
VREF VREF
10-bit
300ksps
ADC
Comparators
VDD
VREF
+-+-
Temp
Sensor
6-bit
IREF
IREF0
GND
Figure 3.1. Detailed EFM8SB2 Block Diagram
P0.n
P1.n
P2.n
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.1 | 4
5 Page 
EFM8SB2 Data Sheet
System Overview
3.8 Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur:
• The core halts program execution.
• Module registers are initialized to their defined reset values unless the bits reset only with a power-on reset.
• External port pins are forced to a known state.
• Interrupts and timers are disabled.
All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power-on reset. The
contents of RAM are unaffected during a reset; any previously stored data is preserved as long as power is not lost. The Port I/O latch-
es are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For Supply Monitor and power-on resets,
the RSTb pin is driven low until the device exits the reset state. On exit from the reset state, the program counter (PC) is reset, and the
system clock defaults to an internal oscillator. The Watchdog Timer is enabled, and program execution begins at location 0x0000.
Reset sources on the device include the following:
• Power-on reset
• External reset pin
• Comparator reset
• Software-triggered reset
• Supply monitor reset (monitors VDD supply)
• Watchdog timer reset
• Missing clock detector reset
• Flash error reset
• RTC0 alarm or oscillator failure
3.9 Debugging
The EFM8SB2 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow flash programming and in-system debug-
ging with the production part installed in the end application. The C2 interface uses a clock signal (C2CK) and a bi-directional C2 data
signal (C2D) to transfer information between the device and a host system. See the C2 Interface Specification for details on the C2
protocol.
3.10 Bootloader
All devices come pre-programmed with a UART bootloader. This bootloader resides in flash and can be erased if it is not needed.
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.1 | 10
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EFM8SB2.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| EFM8SB1 | microcontrollers | Silicon Laboratories |
| EFM8SB2 | microcontrollers | Silicon Laboratories |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |