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LH28F160S3-L 데이터시트 PDF




Sharp에서 제조한 전자 부품 LH28F160S3-L은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 LH28F160S3-L 자료 제공

부품번호 LH28F160S3-L 기능
기능 16M-bit (2MB x 8/1MB x 16) Smart 3 Flash Memories
제조업체 Sharp
로고 Sharp 로고


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LH28F160S3-L 데이터시트, 핀배열, 회로
LH28F160S3-L/S3H-L
LH28F160S3-L/S3H-L
DESCRIPTION
The LH28F16S3-L/S3H-L flash memories with
Smart 3 technology are high-density, low-cost,
nonvolatile, read/write storage solution for a wide
range of applications, having high programming
performance is achieved through high-optimized
page buffer operations. Their symmetrically-blocked
architecture, flexible voltage and enhanced cycling
capability provide for highly flexible component
suitable for resident flash arrays, SIMMs and
memory cards. Their enhanced suspend
capabilities provide for an ideal solution for code +
data storage applications. For secure code storage
applications, such as networking, where code is
either directly executed out of flash or downloaded
to DRAM, the LH28F160S3-L/S3H-L offer three
levels of protection : absolute protection with VPP at
GND, selective hardware block locking, or flexible
software block locking. These alternatives give
designers ultimate control of their code security
needs. The LH28F160S3-L/S3H-L are conformed
to the flash Scalable Command Set (SCS) and the
Common Flash Interface (CFI) specification which
enable universal and upgradable interface, enable
the highest system/device data transfer rates and
minimize device and system-level implementation
costs.
FEATURES
• Smart 3 technology
– 2.7 V or 3.3 V VCC
– 2.7 V, 3.3 V or 5 V VPP
• High speed write performance
– Two 32-byte page buffers
– 2.7 µs/byte write transfer rate
• Common Flash Interface (CFI)
– Universal & upgradable interface
• Scalable Command Set (SCS)
16 M-bit (2 MB x 8/1 MB x 16) Smart 3
Flash Memories (Fast Programming)
• High performance read access time
LH28F160S3-L10/S3H-L10
– 100 ns (3.3±0.3 V)/120 ns (2.7 to 3.6 V)
LH28F160S3-L13/S3H-L13
– 130 ns (3.3±0.3 V)/150 ns (2.7 to 3.6 V)
• Enhanced automated suspend options
– Write suspend to read
– Block erase suspend to write
– Block erase suspend to read
• Enhanced data protection features
– Absolute protection with VPP = GND
– Flexible block locking
– Erase/write lockout during power transitions
• SRAM-compatible write interface
• User-configurable x8 or x16 operation
• High-density symmetrically-blocked architecture
– Thirty-two 64 k-byte erasable blocks
• Enhanced cycling capability
– 100 000 block erase cycles
– 3.2 million block erase cycles/chip
• Low power management
– Deep power-down mode
– Automatic power saving mode decreases ICC
in static mode
• Automated write and erase
– Command user interface
– Status register
• ETOXTMV nonvolatile flash technology
• Packages
– 56-pin TSOP Type I (TSOP056-P-1420)
Normal bend/Reverse bend
– 56-pin SSOP (SSOP056-P-0600)5
[LH28F160S3-L]
– 64-ball CSP (FBGA064-P-0811)
– 64-pin SDIP (SDIP064-P-0750)
ETOX is a trademark of Intel Corporation.
5 Under development
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
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LH28F160S3-L pdf, 반도체, 판매, 대치품
BLOCK DIAGRAM
OUTPUT
BUFFER
DQ0-DQ15
INPUT
BUFFER
LH28F160S3-L/S3H-L
A0-A20
INPUT
BUFFER
Y
DECODER
ADDRESS
LATCH
X
DECODER
ADDRESS
COUNTER
QUERY
ROM
IDENTIFIER
REGISTER
STATUS
REGISTER
DATA
COMPARATOR
Y GATING
32
64 k-BYTE
BLOCKS
MULTIPLEXER
COMMAND
USER
INTERFACE
I/O LOGIC
VCC
BYTE#
CE#
WE#
OE#
RP#
WP#
WRITE STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
STS
VPP
VCC
GND
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LH28F160S3-L 전자부품, 판매, 대치품
erase is suspended and (multi) word/byte write are
inactive, (multi) word/byte write are suspended, or
the device is in deep power-down mode. The other
3 alternate configurations are all pulse mode for
use as a system interrupt.
The access time is 100 ns or 130 ns (tAVQV) at the
VCC supply voltage range of 3.0 to 3.6 V over the
temperature range, 0 to + 70°C (LH28F160S3-L)/
– 40 to +85°C (LH28F160S3H-L). At 2.7 to 3.6 V
VCC, the access time is 120 ns or 150 ns.
The Automatic Power Saving (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical ICCR current is 3 mA at
2.7 V and 3.3 V VCC.
When either CE0# or CE1#, and RP# pins are at
VCC, the ICC CMOS standby mode is enabled.
When the RP# pin is at GND, deep power-down
mode is enabled which minimizes power
consumption and provides write protection during
reset. A reset time (tPHQV) is required from RP#
switching high until outputs are valid. Likewise, the
device has a wake time (tPHEL) from RP#-high until
writes to the CUI are recognized. With RP# at
GND, the WSM is reset and the status register is
cleared.
LH28F160S3-L/S3H-L
1FFFFF
1F0000
1EFFFF
1E0000
1DFFFF
1D0000
1CFFFF
1C0000
1BFFFF
1B0000
1AFFFF
1A0000
19FFFF
190000
18FFFF
180000
17FFFF
170000
16FFFF
160000
15FFFF
150000
14FFFF
140000
13FFFF
130000
12FFFF
120000
11FFFF
110000
10FFFF
100000
0FFFFF
0F0000
0EFFFF
0E0000
0DFFFF
0D0000
0CFFFF
0C0000
0BFFFF
0B0000
0AFFFF
0A0000
09FFFF
090000
08FFFF
080000
07FFFF
070000
06FFFF
060000
05FFFF
050000
04FFFF
040000
03FFFF
030000
02FFFF
020000
01FFFF
010000
00FFFF
000000
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
Fig. 1 Memory Map
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18
17
16
15
14
13
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3
2
1
0
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