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부품번호 SPH0645LM4H-B 기능
기능 I2S Output Digital Microphone
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SPH0645LM4H-B 데이터시트, 핀배열, 회로
SPH0645LM4H-B
SPH0645LM4H-B
Rev B Datasheet
I2S  Output Digital Microphone
The SPH0645LM4H-B is a miniature, low power, bottom port microphone with an I2S digital output.
The solution consists of a proven high performance SiSonic™ acoustic sensor, a serial Analog to
Digital convertor, and an interface to condition the signal into an industry standard 24 bits I2S
format. The I2S interface simplifies the integration in the system and allow direct interconnect to
digital processors, application processors and microcontroller. Saving the need of an external audio
codec, the SPH0645LM4H-B is perfectly suitable for portable applications where size and power
consumption are a constraint.
Product Features:
• High SNR of 65dB(A)
• Low Current of typ. 600µA
• I2S Output: Direct attach to µP
• Multi modes: standard >1MHz,
• 600uA / sleep <900kHz, 10uA
• Flat Frequency Response
• RF Shielded
• Supports Dual Microphones
• Ultra-Stable Performance
• Standard SMD Reflow
• Omnidirectional
• Zero-Height Mic™
• Packaged in SPH 3.50 x 2.65 x 0.98 mm
Typical Applications
• Small portable devices: wearables
• Set-top boxes: TV, gaming, remote controllers
• Smart home devices, Internet of Things,
Connected equipment
SPH0645LM4H-B
Microphone
Filter
I2S
Interface
No Codec
Needed
I2S
Application
Processor
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Datasheet SPH0645LM4H-B Rev B
01




SPH0645LM4H-B pdf, 반도체, 판매, 대치품
Figure 2: Timing Diagram
Parameter
CLK Period
CLK Pulse Width High
CLK Pulse Width Low
WS setup time
Symbol
T
tHC
tLC
tSWS
Min
244.14
85.45
85.45
85.45
Max
488.28
WS hold time
Data Delay from
CLK Rising Edge
Receiver Setup
time
Transmitter Hold Time
Clock Rise Time
Measured from VL to
VH
tHWS
tDC
tsr
thtr
tRC
85.45
178.22
7
65.92
3.75
Unit
ns
ns
ns
ns
ns
ns
Note
35% of min.T(=244.14ns)
35% of min.T(=244.14ns)
WS typically synchronized with CLK falling, should be
equal to tBIL
WS typically synchronized with CLK falling, should be
equal to tBIH
ns
ns
Performance is guaranteed only with SCK edge time
ns <=3.75ns. For slower edge time, operation is guaranteed
but performance degradation might be expected.
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Datasheet SPH0645LM4H-B Rev B
04

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SPH0645LM4H-B 전자부품, 판매, 대치품
Interface Description
The SPH0645LM4H microphone operates as an I2S
slave. The master must provide the BCLK and WS
signals. The Over Sampling Rate is fixed at 64 therefore
the WS signal must be BCLK/64 and synchronized
to the BCLK. Clock frequencies from 2.048Mhz to
4.096MHz are supported so sampling rates from 32KHz
to 64KHz can be had by changing the clock frequency.
The Data Format is I2S, 24 bit, 2’s compliment, MSB
first. The Data Precision is 18 bits, unused bits are zeros.
The SEL pin determines when the microphone drives
the Data pin. When SEL=H the Data pin is driven when
the WS=H, otherwise it is tri-stated (high impedance).
When operating a single microphone on an I2S bus,
a pull down resistor (100K Ohms) should be placed
from the Data pin to ground to insure the bus
capacitance is discharged



     


 
Figure 7: Timing Diagram
System Connections
     

  
Figure 8: System (Stereo) Connections
Notes:
1. Decoupling capacitors (C33, C35) mounted as close as possible are required for optimum SNR.
2. RF filter Capacitors (C32,C34) in the range of 20-200pF may be needed depending on RF environment.
3. If both decoupling and RF filter capacitors are used, the RF filter capacitors should be the closest to the microphone.
4. Detailed information on acoustic, mechanical, and system integration can be found in the latest SiSonic™ Design Guide application note.
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Datasheet SPH0645LM4H-B Rev B
07

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SPH0645LM4H-B

I2S Output Digital Microphone

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