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PDF X9119 Data sheet ( Hoja de datos )
| Número de pieza | X9119 | |
| Descripción | Single Digitally Controlled Potentiometer | |
| Fabricantes | Intersil | |
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Data Sheet
X9119
Single Supply/Low Power/1024-Tap/2-Wire Bus
July 9, 2008
FN8162.4
Single Digitally-Controlled (XDCP™)
Potentiometer
The X9119 integrates a single digitally controlled
potentiometer (XDCP™) on a monolithic CMOS integrated
circuit.
The digital controlled potentiometer is implemented using
1023 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the 2-wire bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and a four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. Powerup recalls the contents of
the default data register (DR0) to the WCR.
The XDCP™ can be used as a three-terminal potentiometer
or as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Functional Diagram
VCC
Features
• 1024 Resistor Taps – 10-Bit Resolution
• 2-Wire Serial Interface for Write, Read, and
Transfer Operations of the Potentiometer
• Wiper Resistance, 40Ω Typical @ VCC = 5V
• Four Non-Volatile Data Registers
• Non-Volatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position on
Power-up.
• Standby Current < 3µA Max
• VCC: 2.7V to 5.5V Operation
• 100kΩ End-to-End Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes Per Bit Per Register
• 14 Ld TSSOP
• Low Power CMOS
• Single Supply Version of the X9118
• Pb-Free available (RoHS compliant)
RH
2-WIRE
BUS
INTERFACE
ADDRESS
DATA
STATUS
BUS
INTERFACE
AND
CONTROL
WRITE
READ
TRANSFER
CONTROL
POWER-ON RECALL
WIPER COUNTER
REGISTER (WCR)
DATA REGISTERS
(DR0-DR3)
WIPER
100kΩ
1024-TAPS
POT
VSS NC NC
RW RL
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners
1 page  
X9119
STOP CONDITION
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 3).
ACKNOWLEDGE
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting eight bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the eight bits of data.
The X9119 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte the X9119 will
respond with a final acknowledge (see Figure 2).
SCL FROM
MASTER
1
89
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ST AR T
FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER
ACKNO WLEDGE
ACKNOWLEDGE POLLING
The disabling of the inputs, during the internal nonvolatile
write operation, can be used to take advantage of the typical
5ms EEPROM write cycle time. Once the stop condition is
issued to indicate the end of the nonvolatile write command
the X9119 initiates the internal write cycle. ACK polling,
Flow 1, can be initiated immediately. This involves issuing
the start condition followed by the device slave address. If
the X9119 is still busy with the write operation, no ACK will
be returned. If the X9119 has completed the write operation,
an ACK will be returned and the master can then proceed
with the next operation.
FLOW 1. ACK Polling Sequence
NONVOLATILE WRITE
COMMAND COMPLETED
ENTERACK POLLING
ISSUE
START
ISSUE SLAVE
ADDRESS
ISSUE STOP
ACK
RETURNED?
YES
NO
FURTHER
OPERATION?
YES
ISSUE
INSTRUCTION
NO
ISSUE STOP
PROCEED
PROCEED
5 FN8162.4
July 9, 2008
5 Page 
X9119
Operating Specifications (Over the recommended operating conditions unless otherwise specified.)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP. MAX.
UNITS
VCC supply current
(active)
ICC1
fSCL = 400kHz; VCC = +5.5V;
SDA = Open; (for 2-wire, Active, Read and
Volatile Write States only)
3 mA
VCC supply current
(nonvolatile write)
ICC2
fSCL = 400kHz; VCC = +5.5V;
SDA = Open; (for 2-wire, Active,
Non-volatile Write State only)
5 mA
VCC current (standby)
ISB VCC = +5.5V; VIN = VSS or VCC;
SDA = VCC;
(for 2-wire, Standby State only)
3 µA
Input leakage current
Output leakage
current
ILI VIN = VSS to VCC
ILO VOUT = VSS to VCC
10 µA
10 µA
Input HIGH voltage
Input LOW voltage
Output LOW voltage
Output HIGH voltage
VIH
VIL
VOL
VOH
IOL = 3mA
VCC x 0.7
-1
VCC + 1
VCC x 0.3
0.4
V
V
V
Endurance and Data Retention
PARAMETER
Minimum Endurance
Data Retention
MIN
100,000
100
UNITS
Data changes per bit per register
years
Capacitance
TEST
Input/Output capacitance (SI)
Input capacitance (SCL, WP, A1 and A0)
SYMBOL
CIN/OUT (Note 6)
CIN (Note 6)
MAX
8
6
UNITS
pF
pF
TEST CONDITIONS
VOUT = 0V
VIN = 0V
Power-Up Timing
PARAMETER
VCC Power-up Rate
Power-up to Initiation of read operation
Power-up to Initiation of write operation
SYMBOL
tr VCC (Note 6)
tPUR (Note 7)
tPUW (Note 7)
MIN
0.2
MAX
50
1
50
UNITS
V/ms
ms
ms
NOTES:
6. Limits should be considered typical and are not production tested.
7. tPUR and tPUW are the delays required from the time the (last) power supply (Vcc-) is stable until the specific instruction can be issued. These
parameters are not 100% tested.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
VCC x 0.1 to VCC x 0.9
10ns
Input and Output Timing Level
VCC x 0.5
11 FN8162.4
July 9, 2008
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet X9119.PDF ] | |
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